US5206862A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for locally deriving test signals from previous response signals
Assignee: Cross-Check Technology Inc
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Filing: 1991-03-08
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Granted: 1993-04-27
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Expires: 2011-03-08
Abstract
Abstract An IC has local test circuitry including a test point array, instruction register, data register, probe line drivers and control/sense line drivers/receivers. To test the IC, the instruction register is loaded initiating the test circuitry to address select test points to receive control signals and to address other select test points at which response signals are to be sensed. Control signals are produced from the data register contents. The data register contents are derived as a function of the prior contents of the data register and a bit pattern formed from response signals of select test points. According to one embodiment, the prior contents are exclusively or'ed with the bit pattern of response signals to derive the new data register contents. A continuous test is performed by using prior response signals exclusively OR'ed to data register contents so as to generate subsequent control signals. Predesigned test sequences enable fast continuous testing of the IC.
Inventors
- 👤 Susheel J. Chandra
- 👤 Tushar Gheewala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:12
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2836; G01R31/2844
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
127 words
A method for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the method comprising the steps of: reading a first plurality of control/sense lines, each one of said first plurality of control/sense line defining a logic state; deriving a second data pattern from said first data pattern and said first plurality of control/sense lines, said second data pattern being stored in said data register; applying a plurality of bits of said second data pattern to a plurality of select test points, respectively.
Claim 2
Independent Claim
127 words
A method for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the method comprising the steps of: reading a first plurality of control/sense lines, each one of said first plurality of control/sense line defining a logic state; deriving a second data pattern from said first data pattern and said first plurality of control/sense lines, said second data pattern being stored in said data register; applying a plurality of bits of said second data pattern to a plurality of select test points, respectively.
Claim 3
Dependent Claim
36 words
The method of claim 1 further comprising, prior to said step of reading, the step of selecting said first plurality of control/sense lines; and prior to said step of applying, selecting a plurality of test points.
Claim 4
Dependent Claim
18 words
The method of claim 2 in which said step of selecting is performed by addressing corresponding probe lines.
Claim 5
Dependent Claim
37 words
The method of claim 1 in which said steps of reading and deriving comprise performing an exclusive "or" operation of said first data pattern and said first plurality of control/sense lines to derive said second data pattern.
Claim 6
Dependent Claim
53 words
The method of claim 1 in which said step of deriving includes complementing the logic state read from one of said first plurality of control/sense lines, and said step of applying includes writing back said complemented signal on said one of said first plurality so that a logic state toggle operation is achieved.
Claim 7
Independent Claim
144 words
A method for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the method comprising the steps of: selecting a first control/sense line having a prescribed logic state and a plurality of second control/sense lines having a different logic state; reading said first control/sense line and said plurality of second control/sense lines into said data register; deriving a second data pattern from the data register contents by shifting said contents in said data register; applying a plurality of bits of said second data pattern to a plurality of select test points, respectively; and repeating said steps of deriving and applying.
Claim 8
Independent Claim
144 words
A method for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the method comprising the steps of: selecting a first control/sense line having a prescribed logic state and a plurality of second control/sense lines having a different logic state; reading said first control/sense line and said plurality of second control/sense lines into said data register; deriving a second data pattern from the data register contents by shifting said contents in said data register; applying a plurality of bits of said second data pattern to a plurality of select test points, respectively; and repeating said steps of deriving and applying.
Claim 9
Independent Claim
134 words
An apparatus for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the apparatus comprising: means for reading a first plurality of control/sense lines, each one of said first plurality of control/sense lines defining a logic state; means for deriving a second data pattern from said first data pattern and said first plurality of control/sense lines, said second data pattern being stored in said data register; means for selecting a plurality of bits of said second data pattern which define respective control signals to be applied to select test points.
Claim 10
Independent Claim
134 words
An apparatus for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the apparatus comprising: means for reading a first plurality of control/sense lines, each one of said first plurality of control/sense lines defining a logic state; means for deriving a second data pattern from said first data pattern and said first plurality of control/sense lines, said second data pattern being stored in said data register; means for selecting a plurality of bits of said second data pattern which define respective control signals to be applied to select test points.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-26 | 1996-10-26 | 1997-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-26 | 2000-10-26 | 2001-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-26 | 2004-10-26 | 2005-04-27 | $7700.00 | Window Closed / Lapsed |