US5930634A
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Method of making an IGFET with a multilevel gate
Assignee: Advanced Micro Devices Inc
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Filing: 1997-04-21
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Granted: 1999-07-27
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Expires: 2017-04-21
Abstract
Abstract A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.
Inventors
- 👤 Frederick N. Hause
- 👤 Robert Dawson
- 👤 H. Jim Fulford, Jr.
- 👤 Mark I. Gardner
- 👤 Mark W. Michael
- 👤 Bradley T. Moore
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D30/60; H10D30/601
Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
166 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a first gate material with a thickness of at most 1000 angstroms on the gate insulator and over the active region; forming a first photoresist layer over the first gate material; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level; removing the first photoresist layer; forming an upper gate level on the lower gate level after removing the first photoresist layer, wherein the multilevel gate includes the upper and lower gate levels; and forming a source and drain in the active region.
Claim 2
Independent Claim
166 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a first gate material with a thickness of at most 1000 angstroms on the gate insulator and over the active region; forming a first photoresist layer over the first gate material; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level; removing the first photoresist layer; forming an upper gate level on the lower gate level after removing the first photoresist layer, wherein the multilevel gate includes the upper and lower gate levels; and forming a source and drain in the active region.
Claim 3
Dependent Claim
47 words
The method of claim 1, including: depositing an insulating layer over the substrate and on the lower gate level after removing the first photoresist layer; polishing the insulating layer until a top surface of the lower gate level is exposed; and then forming the upper gate level.
Claim 4
Dependent Claim
104 words
The method of claim 1, wherein forming the upper gate level includes: depositing a second gate material over the substrate and on the lower gate level; forming a second photoresist layer over the second gate material; irradiating the second photoresist layer with a second image pattern and removing irradiated portions of the second photoresist layer to provide openings above the active region; etching the second gate material through the openings in the second photoresist layer using the second photoresist layer as an etch mask for a portion of the second gate material that forms the upper gate level; and removing the second photoresist layer.
Claim 5
Dependent Claim
32 words
The method of claim 3, wherein the second photoresist layer has a substantially greater thickness than that of the first photoresist layer, and the first and second image patterns are essentially identical.
Claim 6
Dependent Claim
28 words
The method of claim 1, wherein forming the upper gate level includes selectively depositing epitaxial silicon on the lower gate level without depositing epitaxial silicon on the substrate.
Claim 7
Dependent Claim
52 words
The method of claim 1, wherein forming the upper gate level includes: depositing a refractory metal over the substrate and on the lower gate level without depositing refractory metal on the substrate; applying an anneal to form a metal silicide on the lower gate level without forming metal silicide on the substrate.
Claim 8
Dependent Claim
47 words
The method of claim 1, wherein forming the upper gate level includes: depositing an insulating layer over the substrate and the lower gate level; forming a trench partially through the insulating layer that exposes the lower gate level; and depositing a second gate material into the trench.
Claim 9
Dependent Claim
30 words
The method of claim 1, including implanting lightly doped source and drain regions into the active region after forming the lower gate level and before forming the upper gate level.
Claim 10
Dependent Claim
20 words
The method of claim 8, including implanting the lightly doped source and drain regions before removing the first photoresist layer.
Claim 11
Dependent Claim
20 words
The method of claim 8, including implanting the lightly doped source and drain regions after removing the first photoresist layer.
Claim 12
Dependent Claim
35 words
The method of claim 10, wherein implanting the lightly doped source and drain regions includes using the lower gate level as an implant mask that prevents essentially all ions impinging thereon from reaching the substrate.
Claim 13
Dependent Claim
33 words
The method of claim 10, wherein implanting the lightly doped source and drain regions includes implanting ions through the lower gate level into the substrate, thereby providing the IGFET as a depletion-mode device.
Claim 14
Dependent Claim
26 words
The method of claim 1, including implanting lightly doped source and drain regions into the active region using the upper gate level as an implant mask.
Claim 15
Dependent Claim
22 words
The method of claim 1, wherein the upper gate level has a substantially greater thickness than that of the lower gate level.
Claim 16
Dependent Claim
22 words
The method of claim 1, wherein the thickness of the first gate material is in the range of 500 to 1000 angstroms.
Claim 17
Dependent Claim
17 words
The method of claim 1, wherein the multilevel gate has a thickness of at least 2000 angstroms.
Claim 18
Dependent Claim
12 words
The method of claim 1, wherein the lower gate level is polysilicon.
Claim 19
Dependent Claim
26 words
The method of claim 1, wherein the upper gate level is selected from the group consisting of epitaxial silicon, polysilicon, conductive metals, and conductive metal silicides.
Claim 20
Independent Claim
196 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a polysilicon layer with a thickness of at most 1000 angstroms on the gate insulator and over the active region; forming a first photoresist layer over the polysilicon layer; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the polysilicon layer that forms a lower gate level; removing the first photoresist layer; depositing an insulating layer over the substrate and on the lower gate level after removing the first photoresist layer; polishing the insulating layer so that a top surface of the lower gate level is exposed; forming an upper gate level on the lower gate level after polishing the insulating layer, wherein the multilevel gate includes the upper and lower gate levels; and forming a source and drain in the active region.
Claim 21
Independent Claim
196 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a polysilicon layer with a thickness of at most 1000 angstroms on the gate insulator and over the active region; forming a first photoresist layer over the polysilicon layer; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the polysilicon layer that forms a lower gate level; removing the first photoresist layer; depositing an insulating layer over the substrate and on the lower gate level after removing the first photoresist layer; polishing the insulating layer so that a top surface of the lower gate level is exposed; forming an upper gate level on the lower gate level after polishing the insulating layer, wherein the multilevel gate includes the upper and lower gate levels; and forming a source and drain in the active region.
Claim 22
Dependent Claim
114 words
The method of claim 19, wherein forming the upper gate level includes: depositing a conductive material selected from the group consisting of polysilicon and conductive metals on the top surfaces of the lower gate level and the insulating layer; forming a second photoresist layer over the conductive material; irradiating the second photoresist layer with a second image pattern and removing irradiated portions of the second photoresist layer to provide openings above the active region; etching the conductive material through the openings in the second photoresist layer using the second photoresist layer as an etch mask for a portion of the conductive material that forms the upper gate level; and removing the second photoresist layer.
Claim 23
Dependent Claim
22 words
The method of claim 20, wherein the second photoresist layer has a substantially greater thickness than that of the first photoresist layer.
Claim 24
Dependent Claim
15 words
The method of claim 20, wherein the first and second image patterns are essentially identical.
Claim 25
Dependent Claim
28 words
The method of claim 19, wherein forming the upper gate level includes selectively depositing epitaxial silicon on the lower gate level without depositing epitaxial silicon on the substrate.
Claim 26
Dependent Claim
82 words
The method of claim 19, wherein forming the upper gate level includes: depositing a refractory metal on the top surfaces of the lower gate level and insulating layer without depositing the refractory metal on the substrate; applying an anneal to react a portion of the refractory metal with the lower gate level to form a metal silicide as the upper gate level without forming metal silicide on the substrate; and removing an unreacted portion of the refractory metal on the insulating layer.
Claim 27
Dependent Claim
29 words
The method of claim 19, including implanting lightly doped source and drain regions into the active region after forming the lower gate level and before depositing the insulating layer.
Claim 28
Dependent Claim
20 words
The method of claim 25, including implanting the lightly doped source and drain regions before removing the first photoresist layer.
Claim 29
Dependent Claim
20 words
The method of claim 25, including implanting the lightly doped source and drain regions after removing the first photoresist layer.
Claim 30
Dependent Claim
21 words
The method of claim 19, wherein the thickness of the polysilicon layer is in the range of 500 to 1000 angstroms.
Claim 31
Independent Claim
317 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate oxide on the active region; forming a polysilicon layer with a thickness in the range of 500 to 1000 angstroms on the gate oxide and over the active region; forming a first photoresist layer over the polysilicon layer; irradiating the first photoresist layer with an image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the polysilicon layer that forms a lower gate level; removing the first photoresist layer; depositing an insulating layer over the substrate and on the lower gate level after removing the first photoresist layer polishing the insulating layer so that a planar top surface of the lower gate level is exposed and substantially aligned with a planar top surface of the insulating layer; depositing a conductive material on the top surfaces of the lower gate level and the insulating layer, wherein the conductive material has a substantially greater thickness than the polysilicon layer; forming a second photoresist layer over the conductive material, wherein the second photoresist layer has a substantially greater thickness than that of the first photoresist layer; irradiating the second photoresist layer with the image pattern and removing irradiated portions of the second photoresist layer to provide openings above the active region; etching the conductive material through the openings in the second photoresist layer using the second photoresist layer as an etch mask for a portion of the conductive material that forms an upper gate level, wherein the multilevel gate consists of the upper and lower gate levels; removing the second photoresist layer; and forming a source and drain in the active region.
Claim 32
Independent Claim
317 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate oxide on the active region; forming a polysilicon layer with a thickness in the range of 500 to 1000 angstroms on the gate oxide and over the active region; forming a first photoresist layer over the polysilicon layer; irradiating the first photoresist layer with an image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the polysilicon layer that forms a lower gate level; removing the first photoresist layer; depositing an insulating layer over the substrate and on the lower gate level after removing the first photoresist layer polishing the insulating layer so that a planar top surface of the lower gate level is exposed and substantially aligned with a planar top surface of the insulating layer; depositing a conductive material on the top surfaces of the lower gate level and the insulating layer, wherein the conductive material has a substantially greater thickness than the polysilicon layer; forming a second photoresist layer over the conductive material, wherein the second photoresist layer has a substantially greater thickness than that of the first photoresist layer; irradiating the second photoresist layer with the image pattern and removing irradiated portions of the second photoresist layer to provide openings above the active region; etching the conductive material through the openings in the second photoresist layer using the second photoresist layer as an etch mask for a portion of the conductive material that forms an upper gate level, wherein the multilevel gate consists of the upper and lower gate levels; removing the second photoresist layer; and forming a source and drain in the active region.
Claim 33
Dependent Claim
66 words
The method of claim 29, wherein forming the source and drain includes: implanting lightly doped source and drain regions into the active region outside the lower gate level before depositing the conductive material; forming spacers adjacent to opposing sidewalls of the multilevel gate; implanting heavily doped source and drain regions into the active region outside the multilevel gate and the spacers; and applying a high-temperature anneal.
Claim 34
Dependent Claim
38 words
The method of claim 19, wherein: the image pattern defines a critical dimension; and a length of the lower gate level has substantially closer correspondence to the critical dimension than does a length of the upper gate level.
Claim 35
Dependent Claim
25 words
The method of claim 29, wherein the insulating layer is selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and spin-on glass.
Claim 36
Dependent Claim
20 words
The method of claim 29, wherein the conductive material is selected from the group consisting of polysilicon and conductive metals.
Claim 37
Independent Claim
242 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a first gate material on the gate insulator and over the active region; forming a first photoresist layer over the first gate material; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level; removing the first photoresist layer; implanting a lightly doped drain region into the active region, wherein the lightly doped drain region is substantially aligned with a sidewall of the lower gate level; forming an upper gate level on the lower gate level after removing the first photoresist layer and implanting the lightly doped drain region, wherein the multilevel gate includes the upper and lower gate levels; implanting a heavily doped drain region into the active region, wherein the heavily doped drain region is substantially aligned with a sidewall of the upper gate level and substantially spaced from the sidewall of the lower gate level; and forming a source and drain in the active region, wherein the drain includes the lightly doped and heavily doped drain regions.
Claim 38
Independent Claim
242 words
A method of making an IGFET with a multilevel gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a first gate material on the gate insulator and over the active region; forming a first photoresist layer over the first gate material; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level; removing the first photoresist layer; implanting a lightly doped drain region into the active region, wherein the lightly doped drain region is substantially aligned with a sidewall of the lower gate level; forming an upper gate level on the lower gate level after removing the first photoresist layer and implanting the lightly doped drain region, wherein the multilevel gate includes the upper and lower gate levels; implanting a heavily doped drain region into the active region, wherein the heavily doped drain region is substantially aligned with a sidewall of the upper gate level and substantially spaced from the sidewall of the lower gate level; and forming a source and drain in the active region, wherein the drain includes the lightly doped and heavily doped drain regions.
Claim 39
Dependent Claim
47 words
The method of claim 34, including: depositing an insulating layer over the substrate and on the lower gate level after removing the first photoresist layer; polishing the insulating layer until a top surface of the lower gate level is exposed; and then forming the upper gate level.
Claim 40
Dependent Claim
104 words
The method of claim 34, wherein forming the upper gate level includes: depositing a second gate material over the substrate and on the lower gate level; forming a second photoresist layer over the second gate material; irradiating the second photoresist layer with a second image pattern and removing irradiated portions of the second photoresist layer to provide openings above the active region; etching the second gate material through the openings in the second photoresist layer using the second photoresist layer as an etch mask for a portion of the second gate material that forms the upper gate level; and removing the second photoresist layer.
Claim 41
Dependent Claim
22 words
The method of claim 36, wherein the second photoresist layer has a substantially greater thickness than that of the first photoresist layer.
Claim 42
Dependent Claim
47 words
The method of claim 34 wherein forming the upper gate level includes: depositing an insulating layer over the substrate and the lower gate level; forming a trench partially through the insulating layer that exposes the lower gate level; and depositing a second gate material into the trench.
Claim 43
Dependent Claim
33 words
The method of claim 38, including polishing the second gate material until a portion of the second gate material in the trench is substantially aligned with a top surface of the insulating layer.
Claim 44
Dependent Claim
35 words
The method of claim 39, including removing a portion of the insulating layer outside the sidewall of the upper gate level after polishing the second gate material and before implanting the heavily doped drain region.
Claim 45
Dependent Claim
37 words
The method of claim 40, including removing a portion of the gate insulator outside the sidewall of the upper gate level after removing the portion of the insulating layer and before implanting the heavily doped drain region.
Claim 46
Dependent Claim
47 words
The method of claim 34, including implanting the lightly doped drain region using the lower gate level alone as an implant mask for the active region, and implanting the heavily doped drain region using the upper gate level alone as an implant mask for the active region.
Claim 47
Dependent Claim
55 words
The method of claim 34, including implanting a lightly doped source region into the active region simultaneously with implanting the lightly doped drain region, and implanting a heavily doped source region into the active region simultaneously with implanting the heavily doped drain region, wherein the source includes the lightly doped and heavily doped source regions.
Claim 48
Dependent Claim
18 words
The method of claim 34, wherein the lower gate level has a thickness of at most 1000 angstroms.
Claim 49
Dependent Claim
21 words
The method of claim 34, wherein the lower gate level has a thickness in the range of 500 to 1000 angstroms.
Claim 50
Dependent Claim
22 words
The method of claim 34, wherein the upper gate level has a substantially greater thickness than that of the lower gate level.
Claim 51
Dependent Claim
14 words
The method of claim 34, wherein the upper and lower gate levels are polysificon.
Claim 52
Independent Claim
305 words
A method of making an IGFET with a multilevel gate, comprising the following steps in the sequence set forth: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a polysilicon layer with a thickness of at most 1000 angstroms on the gate insulator and over the active region; forming a photoresist layer over the polysilicon layer; irradiating the photoresist layer with an image pattern and removing irradiated portions of the photoresist layer to provide openings above the active region; etching the polysilicon layer through the openings in the photoresist layer using the photoresist layer as an etch mask for a portion of the polysilicon layer that forms a lower gate level; removing the photoresist layer; implanting lightly doped source and drain regions into the active region using the lower gate level alone as an implant mask for the active region, wherein the lightly doped source and drain regions are substantially aligned with opposing sidewalls of the lower gate level; forming an upper gate level on the lower gate level, wherein the upper gate level has a substantially greater thickness than that of the lower gate level, opposing sidewalls of the upper gate level extend laterally beyond the opposing sidewalls of the lower gate level, and the multilevel gate includes the upper and lower gate levels; and implanting a heavily doped source and drain regions into the active region using the upper gate level alone as an implant mask for the active region, wherein the heavily doped source and drain regions are substantially aligned the opposing sidewalls of the upper gate level and substantially spaced from the opposing sidewalls of the lower gate level; wherein a source includes the lightly doped and heavily doped source regions, and a drain includes the lightly doped and heavily doped drain regions.
Claim 53
Independent Claim
305 words
A method of making an IGFET with a multilevel gate, comprising the following steps in the sequence set forth: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a polysilicon layer with a thickness of at most 1000 angstroms on the gate insulator and over the active region; forming a photoresist layer over the polysilicon layer; irradiating the photoresist layer with an image pattern and removing irradiated portions of the photoresist layer to provide openings above the active region; etching the polysilicon layer through the openings in the photoresist layer using the photoresist layer as an etch mask for a portion of the polysilicon layer that forms a lower gate level; removing the photoresist layer; implanting lightly doped source and drain regions into the active region using the lower gate level alone as an implant mask for the active region, wherein the lightly doped source and drain regions are substantially aligned with opposing sidewalls of the lower gate level; forming an upper gate level on the lower gate level, wherein the upper gate level has a substantially greater thickness than that of the lower gate level, opposing sidewalls of the upper gate level extend laterally beyond the opposing sidewalls of the lower gate level, and the multilevel gate includes the upper and lower gate levels; and implanting a heavily doped source and drain regions into the active region using the upper gate level alone as an implant mask for the active region, wherein the heavily doped source and drain regions are substantially aligned the opposing sidewalls of the upper gate level and substantially spaced from the opposing sidewalls of the lower gate level; wherein a source includes the lightly doped and heavily doped source regions, and a drain includes the lightly doped and heavily doped drain regions.
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