US5457060A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufactuirng MOSFET having relatively shallow junction of doped region
Assignee: Winbond Electronics Corp
•
Filing: 1994-06-20
•
Granted: 1995-10-10
•
Expires: 2014-06-20
Abstract
Abstract A process for manufacturing a MOSFET having a shallow junction of a doped region includes preparing an intermediate wafer product, applying an oxide layer on said intermediate wafer product, introducing into a dopant around an interface between said oxide layer and said intermediate wafer product, and driving said dopant into said intermediate wafer product to form a MOSFET having a relatively shallow junction of a doped region. This invention offers a simplified, efficient, and cost-effective process to obtain a MOSFET having a relatively shallow junction of a doped region and being free from electrical leakage possibly occurred at the junction.
Inventors
- 👤 Wen-Yueh Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0181; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S438/00; Y10S438/965
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
121 words
A process for manufacturing a MOSFET having a relatively shallow junction of a doped region comprising the steps of: (a) preparing a wafer as a substrate; (b) growing a field oxide layer on said substrate; (c) growing a gate oxide layer on said substrate; (d) forming a gate on said gate oxide layer to obtain an intermediate wafer product; (e) applying an oxide layer on said gate and gate oxide layer of said intermediate wafer product; (f) introducing a dopant into said gate oxide layer; and (g) driving said dopant into said substrate of said intermediate wafer product to obtain a MOSFET having a relatively shallow junction of a doped region which includes two lightly doped and two heavily doped regions.
Claim 2
Dependent Claim
121 words
A process for manufacturing a MOSFET having a relatively shallow junction of a doped region comprising the steps of: (a) preparing a wafer as a substrate; (b) growing a field oxide layer on said substrate; (c) growing a gate oxide layer on said substrate; (d) forming a gate on said gate oxide layer to obtain an intermediate wafer product; (e) applying an oxide layer on said gate and gate oxide layer of said intermediate wafer product; (f) introducing a dopant into said gate oxide layer; and (g) driving said dopant into said substrate of said intermediate wafer product to obtain a MOSFET having a relatively shallow junction of a doped region which includes two lightly doped and two heavily doped regions.
Claim 3
Dependent Claim
19 words
A process as claimed in claim 1, wherein said wafer is an n-type substrate for fabricating a p-channel transistor.
Claim 4
Dependent Claim
19 words
A process as claimed in claim 1, wherein said wafer is a p-type substrate for fabricating an n-channel transistor.
Claim 5
Dependent Claim
26 words
A process as claimed in claim 3, wherein said p-type substrate is pre-doped with p-type ions to increase a field threshold of said n-channel field transistor.
Claim 6
Dependent Claim
25 words
A process as claimed in claim 1, wherein said gate is made of one selected from the group consisting of polycrystalline silicon and metal silicides.
Claim 7
Dependent Claim
17 words
A process as claimed in claim 1, wherein said step (e) is executed by a deposition process.
Claim 8
Dependent Claim
17 words
A process as claimed in claim 6, wherein said deposition process is a chemical vapor deposition process.
Claim 9
Dependent Claim
18 words
A process as claimed in claim 1, wherein said step (f) is executed by an ion implantation process.
Claim 10
Dependent Claim
18 words
A process as claimed in claim 1, wherein said dopant is an n+ ion for a p-type substrate.
Claim 11
Dependent Claim
18 words
A process as claimed in claim 1, wherein said dopant is an p+ ion for an n-type substrate.
Claim 12
Dependent Claim
18 words
A process as claimed in claim 1, wherein said step (g) is executed by a thermal budget process.
Claim 13
Dependent Claim
18 words
A process as claimed in claim 1, wherein said two lightly doped regions are formed under a gate.
Claim 14
Dependent Claim
19 words
A process as claimed in claim 1, wherein said two heavily doped regions are a source and a drain.
Claim 15
Dependent Claim
141 words
A process for manufacturing a CMOS having a relatively shallow junction of a doped region, comprising the steps of: (a) preparing a wafer as a substrate; (b) forming twin wells in said substrate; (c) forming a p-type ion isolation region on said substrate; (d) growing a field oxide layer on said p-type ion isolation region; (e) growing a gate oxide layer on said substrate; (f) forming a gate on said gate oxide layer to obtain an intermediate wafer product; (g) applying an oxide layer on said gate and gate oxide layer of said intermediate wafer product; (h) introducing a dopant into said gate oxide layer; and (i) driving said dopant into said substrate of said intermediate wafer product to obtain a CMOS having a relatively shallow junction of a doped region which includes two lightly doped and two heavily doped regions.
Claim 16
Dependent Claim
141 words
A process for manufacturing a CMOS having a relatively shallow junction of a doped region, comprising the steps of: (a) preparing a wafer as a substrate; (b) forming twin wells in said substrate; (c) forming a p-type ion isolation region on said substrate; (d) growing a field oxide layer on said p-type ion isolation region; (e) growing a gate oxide layer on said substrate; (f) forming a gate on said gate oxide layer to obtain an intermediate wafer product; (g) applying an oxide layer on said gate and gate oxide layer of said intermediate wafer product; (h) introducing a dopant into said gate oxide layer; and (i) driving said dopant into said substrate of said intermediate wafer product to obtain a CMOS having a relatively shallow junction of a doped region which includes two lightly doped and two heavily doped regions.
Claim 17
Dependent Claim
19 words
A process as claimed in claim 14, wherein said twin wells are an n-type well and a p-type well.
Claim 18
Dependent Claim
30 words
A process as claimed in claim 14, wherein said step (c) is executed by doping p-type ions into said p-type well to increase a field threshold of said p-type well.
Claim 19
Dependent Claim
27 words
A process as claimed in claim 14, wherein said shallow junction of said doped region has a depth ranging from about 0.1 μm to about 0.2 μm.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |