Self-aligned MOSFET gate/source/drain salicide formation

Claim 1

A method of fabricating a MOSFET device structure in a silicon substrate, wherein the MOSFET device structure includes planarized trench isolation field oxide regions formed in the substrate, a layer of gate oxide formed on the substrate to electrically insulate a polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and the gate oxide, LDD N- regions formed in the substrate adjacent the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate, the method comprising the steps of: depositing a layer of polysilicon on the above-defined structure; performing a chemical mechanical polishing (CMP) step to form raised source/drain polysilicon regions that are self-aligned to the LDD N- regions; implanting N-type dopant into the polysilicon gate and into the raised source/drain polysilicon regions; performing a first rapid thermal processing (RTP) step to activate the N-type dopant implant and to diffuse N-type dopant from the raised source/drain polysilicon regions into the underlying LDD N- regions; depositing a layer of cobalt on the polysilicon gate and on the raised source/drain polysilicon regions; implanting heavy ions into the cobalt layer to mix the cobalt and silicon at the interface of the cobalt layer and the underlying polysilicon; depositing a TiN film on the cobalt layer; performing a second RTP step to form cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; removing unreacted cobalt; forming a layer of dielectric material on the structure resulting from the above-recited steps; forming contact openings in the dielectric layer to expose the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; forming a conductive contact layer in the contact opening, and in electrical contact with the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate.

Claim 2

A method of fabricating a MOSFET device structure in a silicon substrate, wherein the MOSFET device structure includes planarized trench isolation field oxide regions formed in the substrate, a layer of gate oxide formed on the substrate to electrically insulate a polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and the gate oxide, LDD N- regions formed in the substrate adjacent the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate, the method comprising the steps of: depositing a layer of polysilicon on the above-defined structure; performing a chemical mechanical polishing (CMP) step to form raised source/drain polysilicon regions that are self-aligned to the LDD N- regions; implanting N-type dopant into the polysilicon gate and into the raised source/drain polysilicon regions; performing a first rapid thermal processing (RTP) step to activate the N-type dopant implant and to diffuse N-type dopant from the raised source/drain polysilicon regions into the underlying LDD N- regions; depositing a layer of cobalt on the polysilicon gate and on the raised source/drain polysilicon regions; implanting heavy ions into the cobalt layer to mix the cobalt and silicon at the interface of the cobalt layer and the underlying polysilicon; depositing a TiN film on the cobalt layer; performing a second RTP step to form cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; removing unreacted cobalt; forming a layer of dielectric material on the structure resulting from the above-recited steps; forming contact openings in the dielectric layer to expose the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; forming a conductive contact layer in the contact opening, and in electrical contact with the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate.