Method of fabricating integrated devices

Claim 1

A method of fabricating an integrated circuit that includes a plurality of non-volatile memory cells comprising the steps of: forming a gate oxide layer on a substrate; depositing a first polysilicon layer on top of said gate oxide; forming a first layer of insulating material overlying said first polysilicon layer; depositing a second layer of polysilicon overlying said first insulating layer; etching a portion of said second polysilicon layer to form a first gate region having a first length in a first direction; etching a portion of said first polysilicon layer to form a second gate region having a second length in said first direction, the second length being longer than said first length in said first direction, said first gate region overlying said second gate region; etching said second polysilicon layer and said first layer of insulating material in portions of locations to expose first portions of said first polysilicon layer and said second polysilicon layer and to not expose other second portions of said first polysilicon layer; and depositing a third layer of polysilicon onto the exposed portions of the first and second polysilicon layers to provide a layer polysilicon physically connecting the first layer of polysilicon and the second layer of polysilicon at locations and doping the exposed polysilicon layer such that some regions of the second polysilicon layer that directly overlie the first polysilicon layer are electrically connected together to form a gate of a MOS transistor at the first regions but the first and second polysilicon layers being electrically insulated from each other at the second regions on the integrated circuit to form a gate structure having a floating gate and a control gate.

Claim 2

A method of fabricating an integrated circuit that includes a plurality of non-volatile memory cells comprising the steps of: forming a gate oxide layer on a substrate; depositing a first polysilicon layer on top of said gate oxide; forming a first layer of insulating material overlying said first polysilicon layer; depositing a second layer of polysilicon overlying said first insulating layer; etching a portion of said second polysilicon layer to form a first gate region having a first length in a first direction; etching a portion of said first polysilicon layer to form a second gate region having a second length in said first direction, the second length being longer than said first length in said first direction, said first gate region overlying said second gate region; etching said second polysilicon layer and said first layer of insulating material in portions of locations to expose first portions of said first polysilicon layer and said second polysilicon layer and to not expose other second portions of said first polysilicon layer; and depositing a third layer of polysilicon onto the exposed portions of the first and second polysilicon layers to provide a layer polysilicon physically connecting the first layer of polysilicon and the second layer of polysilicon at locations and doping the exposed polysilicon layer such that some regions of the second polysilicon layer that directly overlie the first polysilicon layer are electrically connected together to form a gate of a MOS transistor at the first regions but the first and second polysilicon layers being electrically insulated from each other at the second regions on the integrated circuit to form a gate structure having a floating gate and a control gate.

Claim 5

A method of fabricating an integrated circuit that includes a plurality of non-volatile memory cells comprising the steps of: forming a gate oxide layer on a substrate; depositing a first polysilicon layer on top of said gate oxide; forming a first layer of insulating material overlying said first polysilicon layer; etching said first layer of insulating material to expose a portion of the first polysilicon layer at first regions and maintain the layer of insulation at second regions overlying the first polysilicon region; depositing a second layer of polysilicon overlying said first insulating layer and physically contacting the exposed portions of the first polysilicon layer outside the active area of the transistors being formed thereby and being physically insulated from the first polysilicon layer at portions overlying gate regions of transistors; etching a portion of said second polysilicon layer to form a first gate region having a first length in a first direction; etching a portion of said first polysilicon layer to form a plurality of second gate regions having a second length in said first direction, the second length being longer than said first length in said first direction, said first gate region overlying said second gate region; and wherein said plurality of said second gate regions includes regions that are physically connected to the second polysilicon layer by having etched portions of the insulating layer and a plurality of the second gate regions that are electrically insulated from the second polysilicon layers.

Claim 6

A method of fabricating an integrated circuit that includes a plurality of non-volatile memory cells comprising the steps of: forming a gate oxide layer on a substrate; depositing a first polysilicon layer on top of said gate oxide; forming a first layer of insulating material overlying said first polysilicon layer; etching said first layer of insulating material to expose a portion of the first polysilicon layer at first regions and maintain the layer of insulation at second regions overlying the first polysilicon region; depositing a second layer of polysilicon overlying said first insulating layer and physically contacting the exposed portions of the first polysilicon layer outside the active area of the transistors being formed thereby and being physically insulated from the first polysilicon layer at portions overlying gate regions of transistors; etching a portion of said second polysilicon layer to form a first gate region having a first length in a first direction; etching a portion of said first polysilicon layer to form a plurality of second gate regions having a second length in said first direction, the second length being longer than said first length in said first direction, said first gate region overlying said second gate region; and wherein said plurality of said second gate regions includes regions that are physically connected to the second polysilicon layer by having etched portions of the insulating layer and a plurality of the second gate regions that are electrically insulated from the second polysilicon layers.

Claim 10

The method according to claims 1, 4, or 5 in which all portions of the second polysilicon layer on the chip are exposed and none is covered with insulation such that when the third layer of polysilicon is deposited on top of all portions of the second polysilicon layer the second and third layers merge to form a single second layer.

Claim 11

A method of fabricating integrated devices in and on a substrate of semiconductor material, said method comprising steps of: depositing a first polycrystalline silicon layer over said substrate; depositing a layer of insulating material on said first polycrystalline silicon layer; shaping said layer of insulating material for forming insulating portions of insulating material, having a width in a second direction perpendicular to a first direction; depositing at least a second polycrystalline silicon layer on said layer of insulating material wherein said second polycrystalline silicon layer electrically contacts said first polycrystalline silicon layer at least at a portion of said second polycrystalline silicon layer extending from said insulating portions and in said second direction; etching portions of said second polycrystalline silicon layer for forming first gate regions of a first length in said first direction; forming, in said substrate and laterally in relation to said first gate regions, first substrate regions having a first doping level; etching portions of said first polycrystalline silicon layer for forming second gate regions of a second length, greater than said first length, in said first direction; and forming, in said substrate, laterally in relation to said second gate regions, and partially overlapping said first substrate regions, second substrate regions having a second performing level, greater than said first doping level.

Claim 12

A method of fabricating integrated devices in and on a substrate of semiconductor material, said method comprising steps of: depositing a first polycrystalline silicon layer over said substrate; depositing a layer of insulating material on said first polycrystalline silicon layer; shaping said layer of insulating material for forming insulating portions of insulating material, having a width in a second direction perpendicular to a first direction; depositing at least a second polycrystalline silicon layer on said layer of insulating material wherein said second polycrystalline silicon layer electrically contacts said first polycrystalline silicon layer at least at a portion of said second polycrystalline silicon layer extending from said insulating portions and in said second direction; etching portions of said second polycrystalline silicon layer for forming first gate regions of a first length in said first direction; forming, in said substrate and laterally in relation to said first gate regions, first substrate regions having a first doping level; etching portions of said first polycrystalline silicon layer for forming second gate regions of a second length, greater than said first length, in said first direction; and forming, in said substrate, laterally in relation to said second gate regions, and partially overlapping said first substrate regions, second substrate regions having a second performing level, greater than said first doping level.

Claim 14

A method of claims 9 or 10 wherein said step of etching portions of said second polycrystalline silicon layer is followed by the step of etching portions of said layer of insulating material, and said step of forming said first substrate regions is performed by doping ion implantation through said first polycrystalline silicon layer.

Claim 15

A method of claims 9 or 10 wherein said layer of insulating material is formed from dielectric material.

Claim 16

A method of claims 9 or 10 wherein said step of etching portions of said first polycrystalline silicon layer is preceded by the step of forming lateral spacers of insulating material on sides of said first gate regions mutually aligned in said first direction.