US5923682A
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Error correction chip for memory applications
Assignee: Micron Technology Inc
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Filing: 1997-01-29
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Granted: 1999-07-13
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Expires: 2017-01-29
Abstract
Abstract A memory module, such as a SIMM or DIMM, is provided which incorporates error correction circuitry. The error correction circuitry identifies and corrects errors in communications between the memory module and an external processor. A reliable data processing system is also provided, incorporating the memory module comprising the error correction circuitry with a processor. The yield of manufactured chips is increased by presorting the memory chips which make up the memory module, such that a chip with one or more defective cells may be included in a memory module so long as no other chip has defective cells at the same location.
Inventors
- 👤 Mirmajid Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
92 words
A memory module comprising: a plurality of independently addressable memory devices; a communication path for bi-directional data communication between the plurality of independently addressable memory modules and an external circuit; and error correction circuitry electrically located between the plurality of independently addressable memory devices and the communication path, the error correction circuitry operating according to an error correction process, wherein the memory devices are sorted before they are included in the memory module, such that there is zero correlation of failing memory cells among the memory devices in any one memory module.
Claim 2
Dependent Claim
92 words
A memory module comprising: a plurality of independently addressable memory devices; a communication path for bi-directional data communication between the plurality of independently addressable memory modules and an external circuit; and error correction circuitry electrically located between the plurality of independently addressable memory devices and the communication path, the error correction circuitry operating according to an error correction process, wherein the memory devices are sorted before they are included in the memory module, such that there is zero correlation of failing memory cells among the memory devices in any one memory module.
Claim 3
Dependent Claim
24 words
The memory module of claim 1 further comprising a driver unit connected to the plurality of independently addressable memory devices and control signal inputs.
Claim 4
Dependent Claim
17 words
The memory module of claim 2 wherein the error correction circuitry is incorporated into the driver unit.
Claim 5
Dependent Claim
22 words
The memory module of claim 1 wherein the error correction process employs a Hamming code to detect errors in data message transmissions.
Claim 6
Dependent Claim
25 words
The memory module of claim 1 further comprising a circuit board wherein the plurality of independently addressable memory devices are affixed to the circuit board.
Claim 7
Dependent Claim
20 words
The memory module of claim 1 wherein the plurality of independently addressable memory devices comprise dynamic random access memories (DRAMs).
Claim 8
Dependent Claim
100 words
A data processing system comprising: a processor; and a memory module comprising: a plurality of independently addressable memory devices; a communication path for bi-directional data communication between the plurality of independently addressable memory modules and an external circuit; and error correction circuitry electrically located between the plurality of independently addressable memory devices and the communication path, the error correction circuitry operating according to an error correction process, wherein the memory devices are sorted before they are included in the memory module, such that there is zero correlation of failing data bits among the memory devices within any one memory module.
Claim 9
Dependent Claim
100 words
A data processing system comprising: a processor; and a memory module comprising: a plurality of independently addressable memory devices; a communication path for bi-directional data communication between the plurality of independently addressable memory modules and an external circuit; and error correction circuitry electrically located between the plurality of independently addressable memory devices and the communication path, the error correction circuitry operating according to an error correction process, wherein the memory devices are sorted before they are included in the memory module, such that there is zero correlation of failing data bits among the memory devices within any one memory module.
Claim 10
Dependent Claim
25 words
The data processing system of claim 7 further comprising a driver unit connected to the plurality of independently addressable memory devices and control signal inputs.
Claim 11
Dependent Claim
18 words
The data processing system of claim 8 wherein the error correction circuitry is incorporated into the driver unit.
Claim 12
Dependent Claim
26 words
The data processing system of claim 7 further comprising a circuit board wherein the plurality of independently addressable memory devices are affixed to the circuit board.
Claim 13
Dependent Claim
21 words
The data processing system of claim 7 wherein the plurality of independently addressable memory devices comprise dynamic random access memories (DRAMs).
Claim 14
Dependent Claim
22 words
The memory module of claim 7 wherein the error correction process employs a Hamming code to detect errors in data message transmissions.
Claim 15
Independent Claim
90 words
A method of populating a memory module, the memory module having a plurality of independently addressable memory devices and error detection circuitry, comprising the steps of: testing individual memories to determine locations of defective memory cells; selecting a plurality of the individual memories such that there is zero correlation of failing memory cells among the selected plurality of individual memories; and mounting the selected plurality of individual memories on the memory module such that the error detection circuitry is electrically located between the plurality of memories and an external circuit.
Claim 16
Independent Claim
90 words
A method of populating a memory module, the memory module having a plurality of independently addressable memory devices and error detection circuitry, comprising the steps of: testing individual memories to determine locations of defective memory cells; selecting a plurality of the individual memories such that there is zero correlation of failing memory cells among the selected plurality of individual memories; and mounting the selected plurality of individual memories on the memory module such that the error detection circuitry is electrically located between the plurality of memories and an external circuit.
Claim 17
Independent Claim
116 words
A method of error-free communication with a memory module, the memory module comprising a plurality of independently addressable memories and error correction circuitry, the memory module having zero correlation of failing data bits among the memories within the memory module, the method comprising the steps of: writing a data message to the memory module from an external processor, the data message comprising blocks of data bits; receiving the data message at the memory module; modifying the data message using the error correction circuitry by appending check bits to each of the blocks of data bits; and multiplexing the modified data message to the plurality of independently addressable memories using control circuitry provided by the memory module.
Claim 18
Independent Claim
116 words
A method of error-free communication with a memory module, the memory module comprising a plurality of independently addressable memories and error correction circuitry, the memory module having zero correlation of failing data bits among the memories within the memory module, the method comprising the steps of: writing a data message to the memory module from an external processor, the data message comprising blocks of data bits; receiving the data message at the memory module; modifying the data message using the error correction circuitry by appending check bits to each of the blocks of data bits; and multiplexing the modified data message to the plurality of independently addressable memories using control circuitry provided by the memory module.
Claim 19
Dependent Claim
71 words
The method of claim 14, further comprising the steps of: requesting data from the memory module using the external processor; demultiplexing the requested data from the plurality of independently addressable memories using control circuitry provided by the memory module; verifying the requested data message using the error correction circuitry and the appended check bits; correcting any errors in the data message; and transmitting the verified data message to the external processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |