Memory controller with ECC and data streaming control

Claim 3

The method of claim 1 wherein writing the modified data word and the ECC data to the memory subsystem occurs prior to a third occurrence of the STROBE signal.

Claim 4

The method of claim 1 wherein the memory data word has a length, and wherein the first and second I/O data words have a combined length no greater than the length of the memory data word.

Claim 5

The method of claim 3 wherein the length of each I/O data word is 32 bits and wherein the length of the memory data word is 64 bits.

Claim 6

The method of claim 1 wherein retrieving a memory data word comprises: detecting the first occurrence of the STROBE signal; and generating memory subsystem control signals based on the first occurrence of the STROBE signal, to read the memory data word from the memory subsystem.

Claim 7

The method of claim 5 wherein the memory subsystem includes dynamic random access memories (DRAMs) and wherein generating memory subsystem control signals comprises: generating DRAM control signals to read the memory data word from the DRAMs based on the first occurrence of the STROBE signal.

Claim 8

The method of claim 6 wherein generating DRAM control signals comprises: generating row address select (RAS) signals, column address select (CAS) signals, and write enable (WE) signals based on the first occurrence of the STROBE signal.

Claim 9

The method of claim 7 wherein generating DRAM control signals comprises: generating the RAS, CAS, and WE signals so that the DRAMs operate in page mode.

Claim 10

The method of claim 1 wherein the second occurrence of the STROBE signal is within approximately 100 nanoseconds of the first occurrence of the STROBE signal.

Claim 11

The method of claim 1 and further comprising: receiving a starting address from the I/O bus indicative of a starting address for writing the data to the memory subsystem; and performing the steps of reading a memory data word and writing the modified data word based on the starting address.

Claim 12

The method of claim 10 and further comprising: loading the starting address into an address counter, the address counter providing address signals to the memory subsystem based on the address contained in the address counter; and incrementing the address in the address counter based on the STROBE signal.

Claim 15

The method of claim 12 wherein determining a number of memory words comprises: determining the number of words that must be read to align the address boundaries of the memory words read from the memory and the data word received from the I/O bus based on the starting address.

Claim 16

The method of claim 12 and further comprising: generating error correction code (ECC) information corresponding to the modified word; and wherein writing the modified word includes writing the ECC information to the memory.

Claim 17

The method of claim 12 wherein the memory includes memory devices operable in page mode and wherein reading the desired number of memory words comprises: generating memory control signals to perform a page mode read operation on the memory based on the I/O signal.

Claim 18

The method of claim 12 wherein the memory includes memory devices operable in page mode and wherein the step of writing the modified word to the memory comprises: generating memory control signals to perform a page mode write operation on the memory based on the I/O signal.

Claim 19

A memory controller in a computer system having a microprocessor, an input/output (I/O) bus providing a STROBE signal indicative of a time when a data word on the I/O bus is valid, and dynamic random access memory (DRAM), the memory controller comprising: a first data buffer, coupled to the I/O bus, for receiving a first data word from the I/O bus in response to a first occurrence of the STROBE signal; reading means, coupled to the DRAM, for reading and storing a memory word from the DRAM in response to the first occurrence of the STROBE signal; a second data buffer, coupled to the I/O bus, for receiving a second data word from the I/O bus in response to a second occurrence of the STROBE signal; modifying means, coupled to the first and second data buffers and the reading means, for modifying the memory word with the first and second data words to form a write data word; error correction code (ECC) generating means, coupled to the reading means, for generating ECC information corresponding to the write data word; and writing means, coupled to the reading means, for writing the write data word and the corresponding ECC information to the DRAM, the modifying means forming the write data word and the ECC generating means generating the ECC information after the second occurrence of the STROBE signal and the writing means writing the write data word to the DRAM before a third occurrence of the STROBE signal.

Claim 20

A memory controller in a computer system having a microprocessor, an input/output (I/O) bus providing a STROBE signal indicative of a time when a data word on the I/O bus is valid, and dynamic random access memory (DRAM), the memory controller comprising: a first data buffer, coupled to the I/O bus, for receiving a first data word from the I/O bus in response to a first occurrence of the STROBE signal; reading means, coupled to the DRAM, for reading and storing a memory word from the DRAM in response to the first occurrence of the STROBE signal; a second data buffer, coupled to the I/O bus, for receiving a second data word from the I/O bus in response to a second occurrence of the STROBE signal; modifying means, coupled to the first and second data buffers and the reading means, for modifying the memory word with the first and second data words to form a write data word; error correction code (ECC) generating means, coupled to the reading means, for generating ECC information corresponding to the write data word; and writing means, coupled to the reading means, for writing the write data word and the corresponding ECC information to the DRAM, the modifying means forming the write data word and the ECC generating means generating the ECC information after the second occurrence of the STROBE signal and the writing means writing the write data word to the DRAM before a third occurrence of the STROBE signal.

Claim 21

The memory controller of claim 17 wherein the DRAM is operable in page mode and wherein the reading means comprises: means, coupled to the DRAM and receiving the STROBE signal, for generating DRAM control signals to perform a page mode read operation on the DRAM based on the STROBE signal.

Claim 22

The memory controller of claim 17 wherein the DRAM is operable in page mode and wherein the writing means comprises: means, coupled to the DRAM and receiving the STROBE signal, for generating DRAM control signals to perform a page mode write operation on the DRAM in response to the STROBE signal.

Claim 23

The memory controller of claim 17 wherein the first and second data words each contain no more than one half as many bits as the memory word.

Claim 26

The apparatus of claim 21 wherein the generating means generates error correction code (ECC) information corresponding to the modified data word.

Claim 27

The apparatus of claim 21 wherein the generating means generates parity information corresponding to the modified data word.

Claim 28

The apparatus of claim 21 wherein the memory subsystem includes dynamic random access memories (DRAMs) operable in page mode and wherein the reading means comprises: memory control signal generating means for generating memory control signals, based on the STROBE signal from the I/O bus, to perform a page mode read operation on the DRAMs to read the memory data word from the memory subsystem.

Claim 29

The apparatus of claim 21 wherein the memory subsystem includes dynamic random access memories (DRAMs) operable in page mode and wherein the writing means comprises: memory control signal generating means for generating memory control signals, based on the STROBE signal from the I/O bus, to perform a page mode write operation on the DRAMs to write the modified data word and the error detection information to the memory subsystem.

Claim 30

The apparatus of claim 21 wherein the first and second I/O data words each contain no more than one half as many bits as the memory data word.

Claim 31

The apparatus of claim 26 wherein the length of each I/O data word is 32 bits and wherein the length of the memory data word is 64 bits.

Claim 32

The apparatus of claim 26 wherein the length of each I/O data word is 16 bits and wherein the length of the memory data word is 64 bits.