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US4884271A
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US
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Error checking and correcting for read-modified-write operations
Assignee: International Business Machines Corp
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Filing: 1987-12-28
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Granted: 1989-11-28
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Expires: 2007-12-28
Abstract
Abstract Error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits. During each CPU Read cycle, a full word and its ECC bits are read from storage; and a selected 16 data bits are transferred to the CPU directly if they are error free or are corrected by the ECC logic and then transferred if they have only one bit with an error. During each CPU Write cycle, a selected full word and its ECC bits are read from storage; 16 data bits of the word are replaced by 16 data bits from the CPU; ECC bits are calculated for the modified word; and the modified word and its ECC bits are entered into the storage unit so long as no error exists in the remaining 16 bits of the data word which were not replaced/modified. This type of operation is often referred to as a Read-Modify-Write (RMW) cycle. During this RMW operation, the ECC logic detects and corrects a single bit error (if one exists) concurrent with modification of the word and calculation of new ECC bits. The corrected word is then modified by the data bits from the CPU, new ECC bits are calculated and the latter modified word and ECC bits are entered into the storage unit rather than the former word which contained a single bit error. If no error exists, a short RMW cycle is used; if a single bit error exists a longer RMW cycle is used.
Inventors
- 👤 Fernando Concha
- 👤 Charles J. Stancil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:05
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/1056
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
224 words
In a data processing system including a data storage module having a plurality of addressable locations for storing in each said location a digital information segment and an error checking and correcting code (ECC) for said segment and including a processor operating upon information in units smaller than said segment, said system further including read-modify-write (RMW) means for combining a portion of a selected segment with an information unit from the processor to form a new segment and its ECC for transfer to the storage module, the method of transferring information units from the processor to the storage module comprising the steps of concurrently (a) combining a portion of a selected first segment from one of said locations with an information unit from the processor to form a second segment and generating ECC bits for said second segment, and (b) writing said second segment to said one location; (c) determining whether the selected first segment is error free or contains a single bit error; correcting the selected first segment, if it contains a single bit error, to form a third segment; combining a portion of the corrected third segment with the information unit from the processor to form a fourth segment and generating ECC bits for said fourth segment; and rewriting the fourth segment in place of said second segment in said one location.
Claim 2
Dependent Claim
224 words
In a data processing system including a data storage module having a plurality of addressable locations for storing in each said location a digital information segment and an error checking and correcting code (ECC) for said segment and including a processor operating upon information in units smaller than said segment, said system further including read-modify-write (RMW) means for combining a portion of a selected segment with an information unit from the processor to form a new segment and its ECC for transfer to the storage module, the method of transferring information units from the processor to the storage module comprising the steps of concurrently (a) combining a portion of a selected first segment from one of said locations with an information unit from the processor to form a second segment and generating ECC bits for said second segment, and (b) writing said second segment to said one location; (c) determining whether the selected first segment is error free or contains a single bit error; correcting the selected first segment, if it contains a single bit error, to form a third segment; combining a portion of the corrected third segment with the information unit from the processor to form a fourth segment and generating ECC bits for said fourth segment; and rewriting the fourth segment in place of said second segment in said one location.
Claim 3
Dependent Claim
56 words
The method of claim 1 further comprising the steps of determining whether the single bit error lies in or out of said portion of the selected first segment, and maintaining the second segment and its ECC bits rather than the fourth segment in said one location if the single bit error lies out of said portion.
Claim 4
Dependent Claim
384 words
In a data processing system including a data storage module having a plurality of addressable locations for storing in each said location a digital information segment and an error checking and correcting code for said segment and including a processor operating upon information in units smaller than said segment, said system further including read-modify-write (RMW) apparatus including means for reading a selected segment and its ECC from one location, means for combining a portion of the selected segment with an information unit from the processor to form a new segment and for generating an ECC for the new segment for subsequent transfer of the new segment and its ECC into said one location, the improvement comprising in combination with the processor, the storage module and the RMW apparatus; error checking and correcting means coupled to the reading means for receiving the selected segment and its ECC read from the storage module and including first means for determining whether or not the segment is error free or has a single bit error and second means for correcting single bit errors in the segment, control means rendering the determining means effective concurrent with the forming of the new segment and its ECC by the combining and generating means, means effective upon determination of the error free condition of the selected segment for transferring the new segment and its ECC to said one location, means effective upon a determination of a single bit error for transferring the corrected segment to the combining and generating means to form a corrected new segment and its ECC, means thereafter effective for transferring the corrected new segment and its ECC to said one location; a multiplexing/demultiplexing means connected to the processor, apparatus for reading a selected segment and its ECC from one location, means gating the last selected segment directly to the multiplexing/demultiplexing means, said error checking and correcting means determining concurrently with gating of the last segment to the multiplexing/demultiplexing means whether or not the latter segment contains a single bit error, and correcting a single bit error in the latter segment if one exists, means gating the latter corrected segment to the multiplexing/demultiplexing means, and means for providing for the use of the corrected segment by the processor if a single bit error exists in the first selected segment.
Claim 5
Dependent Claim
384 words
In a data processing system including a data storage module having a plurality of addressable locations for storing in each said location a digital information segment and an error checking and correcting code for said segment and including a processor operating upon information in units smaller than said segment, said system further including read-modify-write (RMW) apparatus including means for reading a selected segment and its ECC from one location, means for combining a portion of the selected segment with an information unit from the processor to form a new segment and for generating an ECC for the new segment for subsequent transfer of the new segment and its ECC into said one location, the improvement comprising in combination with the processor, the storage module and the RMW apparatus; error checking and correcting means coupled to the reading means for receiving the selected segment and its ECC read from the storage module and including first means for determining whether or not the segment is error free or has a single bit error and second means for correcting single bit errors in the segment, control means rendering the determining means effective concurrent with the forming of the new segment and its ECC by the combining and generating means, means effective upon determination of the error free condition of the selected segment for transferring the new segment and its ECC to said one location, means effective upon a determination of a single bit error for transferring the corrected segment to the combining and generating means to form a corrected new segment and its ECC, means thereafter effective for transferring the corrected new segment and its ECC to said one location; a multiplexing/demultiplexing means connected to the processor, apparatus for reading a selected segment and its ECC from one location, means gating the last selected segment directly to the multiplexing/demultiplexing means, said error checking and correcting means determining concurrently with gating of the last segment to the multiplexing/demultiplexing means whether or not the latter segment contains a single bit error, and correcting a single bit error in the latter segment if one exists, means gating the latter corrected segment to the multiplexing/demultiplexing means, and means for providing for the use of the corrected segment by the processor if a single bit error exists in the first selected segment.
Claim 6
Dependent Claim
59 words
The system of claim 3 further comprising means determining whether the position of the single bit error lies in or out of said portion of the selected segment, and means effective if the single bit error lies out of said portion for transferring said new segment and its ECC rather than the corrected new segment to said one location.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |