Dynamic memory with error correction on refresh

Claim 1

A memory for correcting stored data during refresh cycles including: dynamic storage array means having data words stored in rows and columns of address locations, data inputs and outputs, address inputs, row address strobe inputs and column address strobe inputs, said storage array means for storing and retrieving data words at selected row and column addresses and for refreshing the data stored in a selected row at predetermined times and for receiving a selected data word from the row being refreshed during each refresh cycle and for correcting it and re-storing it at the same address and for presenting data at said data output from the address selected by signals at said address inputs; an address bus for guiding memory address signals; a clock; refresh counter means coupled to said address inputs and to said clock for supplying sequential addresses to said address inputs during said refresh cycles; means coupled to said address bus and coupled to said row address strobe inputs for supplying said row address strobe signals to said row address strobe inputs; and means coupled to said address bus and coupled to said refresh counter means for supplying column address strobe signals to said column address strobe inputs.

Claim 3

An apparatus for error correcting during the refresh cycle of a dynamic memory comprising: a dynamic memory having address inputs and data input and output, said memory for storing a plurality of data words; means, coupled to said address inputs, for repeatedly refreshing said memory in a plurality of refresh cycles, and for selecting and correcting and re-storing a data word during at least some of said refresh cycles; first row address driver means coupled to said address inputs of said dynamic memory for supplying row address signals to said memory during said refresh cycle; first column address driver means coupled to said address inputs of said memory for supplying column address signals to said memory during said refresh cycle; a clock means for generating pulses indicating the time boundaries of said refresh cycles; a refresh counter means electrically connected to the clock means for counting said clock pulses and generating row and column address signals for coupling by said first row address and column address driver means to said memory during said refresh cycle; an address bus electrically connectable to the column address driver, for guiding memory address signals; second row address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle; and second column address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle.

Claim 4

An apparatus for error correcting during the refresh cycle of a dynamic memory comprising: a dynamic memory having address inputs and data input and output, said memory for storing a plurality of data words; means, coupled to said address inputs, for repeatedly refreshing said memory in a plurality of refresh cycles, and for selecting and correcting and re-storing a data word during at least some of said refresh cycles; first row address driver means coupled to said address inputs of said dynamic memory for supplying row address signals to said memory during said refresh cycle; first column address driver means coupled to said address inputs of said memory for supplying column address signals to said memory during said refresh cycle; a clock means for generating pulses indicating the time boundaries of said refresh cycles; a refresh counter means electrically connected to the clock means for counting said clock pulses and generating row and column address signals for coupling by said first row address and column address driver means to said memory during said refresh cycle; an address bus electrically connectable to the column address driver, for guiding memory address signals; second row address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle; and second column address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle.

Claim 8

An apparatus for error correcting during the refresh cycle of a memory comprising: a dynamic memory having address inputs and data input and output, said memory divided into a plurality of segments, each segment for storing a plurality of data words in a plurality of rows and columns; means, coupled to said address inputs, for repeatedly refreshing said memory in each said element during each of a plurality of refresh cycles, and for selecting and correcting and re-storing a data word from a selected one of said rows being refreshed during said refresh cycles; first row address driver means coupled to said address inputs of said dynamic memory for supplying column address signals to said memory during said refresh cycle; first column address driver means coupled to said address inputs of said memory for supplying column address signals to said memory during said refresh cycle; a clock means for generating pulses indicating the time boundaries of said refresh cycles; a refresh counter means electrically connected to the clock means for counting said clock pulses and generating row and column address signals for coupling by said first row address and column address driver means to said memory during said refresh cycle; an address bus electrically connectable to the column address driver, for guiding memory address signals; second row address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle; and second column address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle.

Claim 9

An apparatus for error correcting during the refresh cycle of a memory comprising: a dynamic memory having address inputs and data input and output, said memory divided into a plurality of segments, each segment for storing a plurality of data words in a plurality of rows and columns; means, coupled to said address inputs, for repeatedly refreshing said memory in each said element during each of a plurality of refresh cycles, and for selecting and correcting and re-storing a data word from a selected one of said rows being refreshed during said refresh cycles; first row address driver means coupled to said address inputs of said dynamic memory for supplying column address signals to said memory during said refresh cycle; first column address driver means coupled to said address inputs of said memory for supplying column address signals to said memory during said refresh cycle; a clock means for generating pulses indicating the time boundaries of said refresh cycles; a refresh counter means electrically connected to the clock means for counting said clock pulses and generating row and column address signals for coupling by said first row address and column address driver means to said memory during said refresh cycle; an address bus electrically connectable to the column address driver, for guiding memory address signals; second row address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle; and second column address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle.

Claim 12

An apparatus for error correcting during the refresh cycle of a memory including: a dynamic memory having address inputs divided into a plurality of segments, each segment for storing a plurality of data words at a plurality of row and column addresses; a cache memory coupled to said dynamic memory for receiving and storing a data word from each said segment of said memory when said data word is addressed and is not already stored in said cache memory; refreshing means coupled to said dynamic memory for repeatedly refreshing one row in each said segment during each of a plurality of refresh cycles and for selecting and correcting and re-storing a data word from a selected one of said rows being refreshed during each said refresh cycle; means for signalling when said selecting and correcting means has found an error during a refresh cycle; first row address driver means coupled to said address inputs of said dynamic memory for supplying row address signals to said memory during said refresh cycle; first column address driver means coupled to said address inputs of said memory for supplying column address signals to said memory during said refresh cycle; a clock means for generating pulses indicating the time boundaries of said refresh cycles; a refresh counter means, electrically connected to the selecting and correcting means, for counting said clock pulses and generating row and column address signals for coupling by said first row address and column address driver means to said memory during said refresh cycle; an address bus electrically connectable to the column address driver for guiding memory address signals; second row address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle; and second column address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle.

Claim 13

An apparatus for error correcting during the refresh cycle of a memory including: a dynamic memory having address inputs divided into a plurality of segments, each segment for storing a plurality of data words at a plurality of row and column addresses; a cache memory coupled to said dynamic memory for receiving and storing a data word from each said segment of said memory when said data word is addressed and is not already stored in said cache memory; refreshing means coupled to said dynamic memory for repeatedly refreshing one row in each said segment during each of a plurality of refresh cycles and for selecting and correcting and re-storing a data word from a selected one of said rows being refreshed during each said refresh cycle; means for signalling when said selecting and correcting means has found an error during a refresh cycle; first row address driver means coupled to said address inputs of said dynamic memory for supplying row address signals to said memory during said refresh cycle; first column address driver means coupled to said address inputs of said memory for supplying column address signals to said memory during said refresh cycle; a clock means for generating pulses indicating the time boundaries of said refresh cycles; a refresh counter means, electrically connected to the selecting and correcting means, for counting said clock pulses and generating row and column address signals for coupling by said first row address and column address driver means to said memory during said refresh cycle; an address bus electrically connectable to the column address driver for guiding memory address signals; second row address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle; and second column address driver means coupled to said address inputs of said memory and for coupling to said address bus for driving said address inputs of said memory with signals from said address bus when said memory is not in a refresh cycle.