US4926426A
Expired / Lapsed
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Error correction check during write cycles
Assignee: Unisys Corp
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Filing: 1988-08-30
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Granted: 1990-05-15
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Expires: 2008-08-30
Abstract
Abstract An error correcting check of a memory system is provided when a memory in which the Dynamic Random Access Memory (DRAM) is of the type which has input lines that are directly coupled to its output lines. Utilizing this type of DRAM, the memory system employs controls, input, output and read circuitry to read bits out of the memory via the output circuitry and write circuitry to write bits into the memory via the input circuitry. An error checking and correction circuit is coupled to the output means which includes a check bit generator and a syndrome generator, and a control means energizes the error checking and correcting means during the write cycle, as well as the read cycle, so that the errors are detected during the write cycle as well as the read cycle. In this manner, errors which occur in circuitry other than the memory, which includes the memory driving and reading logic and also the check bit generator logic translators and syndrome generators, may be separately detected from memory errors.
Inventors
- 👤 James H. Scheuneman
- 👤 Michael E. Mayer
- 👤 David M. Purdham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:32
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076; G06F11/22; G06F11/2205; G06F11/2215
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
266 words
In a memory system comprising memory means for storing digital bits, input means coupled to said memory means for supplying bits to said memory means, output means coupled to said memory means for receiving bits from said memory means, write means for writing selected bits from said input means into said memory means during a write cycle, read means for reading selected bits out of said memory means to said output means during a read cycle, error checking and correction means coupled to said output means for checking and correcting errors upon the occurrence of said selected bits at said output means, control means coupled to said memory means to control the writing of selected bits into said memory means and the reading of selected bits from said memory means, syndrome generating means coupled to said output means for developing a syndrome code representative of said selected bits of said output means, and coupling means for coupling selected bits to be written into said memory means during write cycles to said error checking and correction means in a manner that bypasses said selected bits from said memory means, the improvement wherein said syndrome generating means is operable during during both read and write cycles, and said memory system further comprises status means coupled to said control means and to said syndrome generating means for indicating when an error is detected if said error occurred during a read cycle or during a write cycle, and for isolating errors which are generated in said memory means from errors which are generated in other elements of said memory system.
Claim 2
Dependent Claim
266 words
In a memory system comprising memory means for storing digital bits, input means coupled to said memory means for supplying bits to said memory means, output means coupled to said memory means for receiving bits from said memory means, write means for writing selected bits from said input means into said memory means during a write cycle, read means for reading selected bits out of said memory means to said output means during a read cycle, error checking and correction means coupled to said output means for checking and correcting errors upon the occurrence of said selected bits at said output means, control means coupled to said memory means to control the writing of selected bits into said memory means and the reading of selected bits from said memory means, syndrome generating means coupled to said output means for developing a syndrome code representative of said selected bits of said output means, and coupling means for coupling selected bits to be written into said memory means during write cycles to said error checking and correction means in a manner that bypasses said selected bits from said memory means, the improvement wherein said syndrome generating means is operable during during both read and write cycles, and said memory system further comprises status means coupled to said control means and to said syndrome generating means for indicating when an error is detected if said error occurred during a read cycle or during a write cycle, and for isolating errors which are generated in said memory means from errors which are generated in other elements of said memory system.
Claim 3
Dependent Claim
42 words
In a memory system as claimed in claim 1, the further improvement wherein said error checking and correction means comprises parity checking means that are isolated from said status means for more precisely determining the origin of errors in said memory system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |