US4453248A
Expired / Lapsed
US
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Fault alignment exclusion method to prevent realignment of previously paired memory defects
Assignee: International Business Machines Corp
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Filing: 1982-06-16
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Granted: 1984-06-05
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Expires: 2002-06-16
Abstract
Abstract A method is disclosed for insuring that two semiconductor chips which have a 1-bit defect at the same chip address are not paired at any memory address by a fault alignment exclusion mechanism (FAEM) which functions to position chips having defects at different memory addresses. The FAEM employs an error map to determine which chips must be realigned in their respective columns and an address permute vector functions to effectively change the physical address of the chip in the column to a logical address. The two permute vectors for the two columns contributing to any uncorrectable error are "exclusive-ORed" and the result stored in a second map along with an identification of the chip columns. Any time in the future that a new permute vector is proposed for assignment to any column of chips, the changed permute vector is exclusive-ORed with the permute vectors currently assigned to all other columns of the memory to see if any such combination produces a result forbidden by the forbidden result table. If no such forbidden result is found, the proposed permute vector can be assigned with the assurance that no pair of chips previously found to produce aligned faults will align now in any row of the memory. If any forbidden result is found, the proposed permute vector is discarded and a new one proposed.
Inventors
- 👤 Philip M. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:45
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
251 words
In a memory system which employs permute vectors for each column of the memory array to selectively rearrange within the columns the logical order of individual memory chips so as to permit a pair of chips containing defective bit positions at the same address to be relatively repositioned so that said same address contains only one defective bit position, a method for generating a new permute vector for one of said columns, said method being characterized by: (1) generating a result vector by combining the two initial permute vectors associated with the two columns containing chips having defects which contributed to the unexpected uncorrectable error, said result vector representing a constant relationship between the permute vectors assigned to said two columns when said chips are aligned in the same row of said matrix; (2) storing said result vector with paired column identification data; (3) developing a new permute vector for one of said two columns to rearrange the order of said chips in said one column; (4) combining said new permute vector with the current permute vector of each said other column which is listed in said table as paired with said one column to produce a new result vector for each said pair; (5) comparing each said new result vector with each stored result vector associated with correspondingly paired columns and, depending on the result of said comparison: (a) returning to step 3; or (b) assigning said new permute vector to said column for future use in said memory system.
Claim 2
Dependent Claim
251 words
In a memory system which employs permute vectors for each column of the memory array to selectively rearrange within the columns the logical order of individual memory chips so as to permit a pair of chips containing defective bit positions at the same address to be relatively repositioned so that said same address contains only one defective bit position, a method for generating a new permute vector for one of said columns, said method being characterized by: (1) generating a result vector by combining the two initial permute vectors associated with the two columns containing chips having defects which contributed to the unexpected uncorrectable error, said result vector representing a constant relationship between the permute vectors assigned to said two columns when said chips are aligned in the same row of said matrix; (2) storing said result vector with paired column identification data; (3) developing a new permute vector for one of said two columns to rearrange the order of said chips in said one column; (4) combining said new permute vector with the current permute vector of each said other column which is listed in said table as paired with said one column to produce a new result vector for each said pair; (5) comparing each said new result vector with each stored result vector associated with correspondingly paired columns and, depending on the result of said comparison: (a) returning to step 3; or (b) assigning said new permute vector to said column for future use in said memory system.
Claim 3
Dependent Claim
32 words
The method recited in claim 1 in which said step of generating said result vector by combining the two permute vectors and said combining of step 4 involves an exclusive-OR logical operation.
Claim 4
Dependent Claim
39 words
The method recited in claim 1 in which said step of generating said result vector by combining the two permute vectors and said combining of step 4 involves a subtraction of the value of the said two permute vectors.
Claim 5
Dependent Claim
23 words
The method recited in claim 1 in which said step of storing said result vector establishes a table in memory which is cumulative.
Claim 6
Dependent Claim
53 words
The method recited in claim 4 in which said step of developing new permute vectors for one of said columns involves developing a new permute vector for the other column when the results of step 5a causes a return to step 3 until all possible combinations specified in step 4 have been exhausted.
Claim 7
Dependent Claim
28 words
The method recited in claim 5 further characterized by the step of updating an error map stored in a memory which reflects defective bit positions in said memory.
Claim 8
Dependent Claim
81 words
The method recited in claim 6 in which the normal operation of said memory in storing user data is momentarily interrupted to generate a new permute vector in response to the memory system providing an indication that an uncorrectable error has occurred at an address position and is further characterized by the additional step of rearranging user stored data in said one column to which the newly developed permute vector is assigned prior to returning said memory to an online operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-05 | 1987-12-05 | 1988-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-05 | 1991-12-05 | 1992-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-05 | 1995-12-05 | 1996-06-05 | $7700.00 | Window Closed / Lapsed |