US5923567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and device for test vector analysis
Assignee: Altera Corp
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Filing: 1996-10-09
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Granted: 1999-07-13
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Expires: 2016-10-09
Abstract
Abstract A method and device for testing and manufacturing integrated circuits such as microprocessors, memories, ASICs, programmable logic, and other types of integrated circuits. A test system is designed to test the relevant integrated circuit. A device under test emulator responds to the test system. If modifications are needed, the test system can be modified, and used to test actual devices.
Inventors
- 👤 Tajana Simunic
- 👤 Naresh U. Mehta
- 👤 Caleb Crome
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:31
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G01R31/318307; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
71 words
A method of making integrated circuits comprising the steps of: designing an integrated circuit; developing a test process for said integrated circuit; simulating a response of said integrated circuit to said test process; modifying said test process or the circuit design in response to said step of simulating a response of said integrated circuit; fabricating an actual integrated circuit; and using said modified test process to test said actual integrated circuit.
Claim 2
Independent Claim
71 words
A method of making integrated circuits comprising the steps of: designing an integrated circuit; developing a test process for said integrated circuit; simulating a response of said integrated circuit to said test process; modifying said test process or the circuit design in response to said step of simulating a response of said integrated circuit; fabricating an actual integrated circuit; and using said modified test process to test said actual integrated circuit.
Claim 3
Dependent Claim
26 words
The method as recited in claim 1 wherein said step of simulating a response is a step of simulating said integrated circuit in a circuit simulator.
Claim 4
Dependent Claim
21 words
The method as recited in claim 2 wherein said circuit simulator simulates a schematic of an integrated circuit using a netlist.
Claim 5
Dependent Claim
16 words
The method as recited in claim 1 wherein said integrated circuit is a programmable logic device.
Claim 6
Dependent Claim
14 words
The method as recited in claim 1 wherein said integrated circuit is a microprocessor.
Claim 7
Dependent Claim
89 words
A semiconductor system comprising: a semiconductor device test system, said test system programmed to apply test signals to a device under test and monitor a response of said device under test to said test signals; and a device under test emulator, said device under test emulator mimicking an expected response of said device under test, and supplying to the semiconductor test system for development of said test system programming before fabrication of the integrated circuit and the test system programming is used for testing the integrated circuit after fabrication.
Claim 8
Dependent Claim
89 words
A semiconductor system comprising: a semiconductor device test system, said test system programmed to apply test signals to a device under test and monitor a response of said device under test to said test signals; and a device under test emulator, said device under test emulator mimicking an expected response of said device under test, and supplying to the semiconductor test system for development of said test system programming before fabrication of the integrated circuit and the test system programming is used for testing the integrated circuit after fabrication.
Claim 9
Dependent Claim
17 words
The semiconductor system as recited in claim 6 wherein said device test system comprises a wafer probe.
Claim 10
Dependent Claim
76 words
Software on a computer readable storage medium comprising: a receiving element for receiving test vectors from an integrated circuit test system; a simulation element for modeling response of an integrated circuit to said test vectors; a reporting element for reporting a response of said simulation element to said test vectors; and a hardware interface for applying a modified test process using said simulation element before said integrated circuit is fabricated, to said integrated circuit after fabrication.
Claim 11
Dependent Claim
76 words
Software on a computer readable storage medium comprising: a receiving element for receiving test vectors from an integrated circuit test system; a simulation element for modeling response of an integrated circuit to said test vectors; a reporting element for reporting a response of said simulation element to said test vectors; and a hardware interface for applying a modified test process using said simulation element before said integrated circuit is fabricated, to said integrated circuit after fabrication.
Claim 12
Dependent Claim
27 words
Software as recited in claim 8 further comprising a license server, said license server determining if a said simulation element is available for processing said test vectors.
Claim 13
Dependent Claim
28 words
Software as recited in claim 8 wherein said software selectively applies and test vectors to said simulation element or said fabricated integrated circuit with a common user interface.
Claim 14
Dependent Claim
32 words
Software as recited in claim 8 wherein said software selectively applies said test vectors to said simulation element, said fabricated integrated circuit, or both said simulation element and said fabricated integrated circuit.
Claim 15
Dependent Claim
17 words
Software as recited in claim 8 wherein said simulation element comprises a netlist of said integrated circuit.
Claim 16
Independent Claim
51 words
A method of making an integrated circuit comprising: providing a design of the integrated circuit; providing an emulation model of the integrated design; developing a test process for the integrated circuit using the emulation model before fabrication of integrated circuit; and using the test process on the integrated circuit after fabrication.
Claim 17
Independent Claim
51 words
A method of making an integrated circuit comprising: providing a design of the integrated circuit; providing an emulation model of the integrated design; developing a test process for the integrated circuit using the emulation model before fabrication of integrated circuit; and using the test process on the integrated circuit after fabrication.
Claim 18
Dependent Claim
33 words
The integrated circuit of claim 13 wherein a state of a hardware switch determines whether the test process is used on the emulation model of the integrated circuit or the fabricated integrated circuit.
Claim 19
Dependent Claim
15 words
The integrated circuit of claim 13 wherein the test process is a computer software program.
Claim 20
Dependent Claim
29 words
The integrated circuit of claim 13 wherein the test process processes responses from the emulation model of the integrated circuit and the fabricated integrated circuit in a similar fashion.
Claim 21
Dependent Claim
15 words
The integrated circuit of claim 13 wherein the integrated circuit is a programmable logic device.
Claim 22
Dependent Claim
26 words
The integrated circuit of claim 13 wherein responses of the emulation model of the integrated circuit are provided to the test process via a first server.
Claim 23
Dependent Claim
24 words
The integrated circuit of claim 18 wherein the responses of the fabricated integrated circuit are provided to the test process via a second server.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |