US5539652A
Expired / Lapsed
US
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Method for manufacturing test simulation in electronic circuit design
Assignee: Keysight Technologies Inc
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Filing: 1995-02-07
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Granted: 1996-07-23
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Expires: 2015-02-07
Abstract
Abstract A manufacturing and test simulation method for electronic circuit design integrated with computer aided design tools to provide concurrent engineering of manufacturing and testability aspects of a product concurrent with the functional design of a product. The manufacturing and test simulator (MTSIM) simulates manufacturing test and repair aspects of boards and multichip modules (MCMs) from design concept through manufacturing release to aid the designer in selecting appropriate trade-offs in the design for manufacturability and the design for testability. All simulation by the methods of the present invention applies manufacturing and test models down to the component level. The methods of the simulator include a new yield model for boards and MCMs which accounts for the clustering of solder defects. MTSIM models solder faults, manufacturing workmanship faults, component performance faults, and reliability faults. Fault probabilities for the circuit design are estimated based on the component type, the component functionality, and the assembly process used. Up to seven manufacturing test steps can be simulated by MTSIM. Test coverage models will support all commonly used manufacturing test methodologies, including visual inspection, in-circuit test, IEEE 1149.1 boundary scan, selftest, diagnostics, and burn-in. Pareto and iterative "what-if" analysis may be used to locate particular enhancements which most benefit the manufacturability and testability of the product.
Inventors
- 👤 Mauro V. Tegethoff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:46
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/333; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2836; G01R31/2846; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318591; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/20; G06F2111/00; G06F2111/08; G06F2119/00; G06F2119/22
Claims Analysis
Total Claims: 64
Claim 1
Independent Claim
94 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of: providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; providing a description of a manufacturing test process; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes.
Claim 2
Independent Claim
94 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of: providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; providing a description of a manufacturing test process; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes.
Claim 3
Dependent Claim
64 words
The method of claim 1 wherein the step of simulating further comprises the steps of: estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component; and simulating application of said manufacturing test process to said incoming fault probability value to estimate said manufacturing test and quality attributes.
Claim 4
Dependent Claim
40 words
The method of claim 2 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
Claim 5
Dependent Claim
111 words
The method of claim 2 wherein the step of simulating application of said manufacturing test process further comprises the steps of: estimating the average number of defects (Do) in said electronic assembly as: ##EQU37## where: Pfi j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly, TC j is a test coverage value corresponding to the j'th said component in said electronic assembly, and N is the number of components in said electronic assembly; and estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
Claim 6
Dependent Claim
59 words
The method of claim 4 wherein the incoming fault probability value (Pfi) of said j'th component is determined as: Pfi=1-(1-fp).sup.n where: n is the number of trials for a fault type in a component and is derived from said pre-determined test and quality information, fp is the fault probability and is derived from said pre-determined test and quality information.
Claim 7
Dependent Claim
35 words
The method of claim 4 wherein yield (Y) is determined as: Y=Ycl+Yncl where: Ycl is a yield determined from clustered solder defects, and Yncl is a yield determined from non-clustered assembly defects and functional defects.
Claim 8
Dependent Claim
18 words
The method of claim 6 wherein said Ycl is determined as: ##EQU38## where: α is the clustering factor.
Claim 9
Dependent Claim
56 words
The method of claim 7 further comprising the step of: providing information relating to the assembly process used for said electronic assembly; estimating the clustering factor (α) as: ##EQU39## where: μ is the mean number of defects for said assembly process, and σ is the standard deviation of said number of defects for said assembly process.
Claim 10
Dependent Claim
12 words
The method of claim 6 wherein said Yncl is determined as: Yncl=e.sup.-Do
Claim 11
Dependent Claim
81 words
The method of claim 4: wherein said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly.
Claim 12
Dependent Claim
57 words
The method of claim 1 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect a contribution of each component to said manufacturing test and quality attributes.
Claim 13
Dependent Claim
65 words
The method of claim 1 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
Claim 14
Dependent Claim
62 words
The method of claim 1 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
Claim 15
Independent Claim
234 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of: (a) providing a description of the design of said electronic assembly; (b) providing pre-determined test and quality information relating to each component in said electronic assembly; (c) providing a description of a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps; (d) estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps; (e) assigning the first of said sequential test steps as the current test step; (f) simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes; (g) determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of step (f); (h) assigning the next of said sequential test steps as the current test step; and (h) repeating steps (f) and (g) and (h) for each of said plurality of test steps of said manufacturing test process.
Claim 16
Independent Claim
234 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of: (a) providing a description of the design of said electronic assembly; (b) providing pre-determined test and quality information relating to each component in said electronic assembly; (c) providing a description of a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps; (d) estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps; (e) assigning the first of said sequential test steps as the current test step; (f) simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes; (g) determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of step (f); (h) assigning the next of said sequential test steps as the current test step; and (h) repeating steps (f) and (g) and (h) for each of said plurality of test steps of said manufacturing test process.
Claim 17
Dependent Claim
40 words
The method of claim 14 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
Claim 18
Dependent Claim
111 words
The method of claim 14 wherein the step of simulating application of said manufacturing test process further comprises the steps of: estimating the average number of defects (Do) in said electronic assembly as: ##EQU40## where: Pfi j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly, TC j is a test coverage value corresponding to the j'th said component in said electronic assembly, and N is the number of components in said electronic assembly; and estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
Claim 19
Dependent Claim
60 words
The method of claim 16 wherein the incoming fault probability value (Pfi) of said j'th component is determined as: Pfi=1-(1-fp).sup.n where: n is the number of trials for the a fault type of a component and is derived from said pre-determined test and quality information, fp is the fault probability and is derived from said pre-determined test and quality information.
Claim 20
Dependent Claim
36 words
The method of claim 16 wherein a yield (Y) is determined as: Y=Ycl+Yncl where: Ycl is a yield determined from clustered solder defects, and Yncl is a yield determined from non-clustered assembly defects and functional defects.
Claim 21
Dependent Claim
18 words
The method of claim 18 wherein said Ycl is determined as: ##EQU41## where: α is the clustering factor.
Claim 22
Dependent Claim
56 words
The method of claim 19 further comprising the step of: providing information relating to the assembly process used for said electronic assembly; estimating the clustering factor (α) as: ##EQU42## where: μ is the mean number of defects for said assembly process, and σ is the standard deviation of said number of defects for said assembly process.
Claim 23
Dependent Claim
12 words
The method of claim 18 wherein said Yncl is determined as: Yncl=e.sup.-Do
Claim 24
Dependent Claim
90 words
The method of claim 16: wherein each test step of said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly of said current test step.
Claim 25
Dependent Claim
20 words
The method of claim 14 wherein the outgoing fault probability value (Pfo) of said j'th component is determined as: Pfo=1-(1-Pfi).sup.1-TC)
Claim 26
Dependent Claim
58 words
The method of claim 14 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect to a contribution of each component to said manufacturing test and quality attributes.
Claim 27
Dependent Claim
65 words
The method of claim 14 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
Claim 28
Dependent Claim
62 words
The method of claim 14 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
Claim 29
Independent Claim
94 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing test process, said method comprising the steps of: providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process.
Claim 30
Independent Claim
94 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing test process, said method comprising the steps of: providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process.
Claim 31
Dependent Claim
64 words
The method of claim 27 wherein the step of simulating further comprises the steps of: estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component; and simulating application of said manufacturing test process to said incoming fault probability value to estimate said manufacturing test and quality attributes.
Claim 32
Dependent Claim
40 words
The method of claim 28 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
Claim 33
Dependent Claim
111 words
The method of claim 28 wherein the step of simulating application of said manufacturing test process further comprises the steps of: estimating the average number of defects (Do) in said electronic assembly as: ##EQU43## where: Pfi j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly, TC j is a test coverage value corresponding to the j'th said component in said electronic assembly, and N is the number of components in said electronic assembly; and estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
Claim 34
Dependent Claim
59 words
The method of claim 30 wherein the incoming fault probability value (Pfi) of said j'th component is determined as: Pfi=1-(1-fp).sup.n where: n is the number of trials for a fault type of a component and is derived from said pre-determined test and quality information, fp is the fault probability and is derived from said pre-determined test and quality information.
Claim 35
Dependent Claim
36 words
The method of claim 30 wherein a yield (Y) is determined as: Y=Ycl+Yncl where: Ycl is a yield determined from clustered solder defects, and Yncl is a yield determined from non-clustered assembly defects and functional defects.
Claim 36
Dependent Claim
18 words
The method of claim 32 wherein said Ycl is determined as: ##EQU44## where: α is the clustering factor.
Claim 37
Dependent Claim
56 words
The method of claim 33 further comprising the step of: providing information relating to the assembly process used for said electronic assembly; estimating the clustering factor (α) as: ##EQU45## where: μ is the mean number of defects for said assembly process, and σ is the standard deviation of said number of defects for said assembly process.
Claim 38
Dependent Claim
12 words
The method of claim 32 wherein said Yncl is determined as: Yncl=e.sup.-Do
Claim 39
Dependent Claim
81 words
The method of claim 30: wherein said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly.
Claim 40
Dependent Claim
58 words
The method of claim 27 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect to a contribution of each component to said manufacturing test and quality attributes.
Claim 41
Dependent Claim
65 words
The method of claim 27 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
Claim 42
Dependent Claim
62 words
The method of claim 27 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
Claim 43
Independent Claim
102 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing assembly process, said method comprising the steps of: providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; providing a description of a manufacturing test process; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process.
Claim 44
Independent Claim
102 words
A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing assembly process, said method comprising the steps of: providing a description of the design of said electronic assembly; providing pre-determined test and quality information relating to each component in said electronic assembly; providing a description of a manufacturing test process; and simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process.
Claim 45
Dependent Claim
64 words
The method of claim 40 wherein the step of simulating further comprises the steps of: estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component; and simulating application of said manufacturing test process to said incoming fault probability value to estimate said manufacturing test and quality attributes.
Claim 46
Dependent Claim
40 words
The method of claim 41 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
Claim 47
Dependent Claim
111 words
The method of claim 41 wherein the step of simulating application of said manufacturing test process further comprises the steps of: estimating the average number of defects (Do) in said electronic assembly as: ##EQU46## where: Pfi j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly, TC j is a test coverage value corresponding to the j'th said component in said electronic assembly, and N is the number of components in said electronic assembly; and estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
Claim 48
Dependent Claim
59 words
The method of claim 43 wherein the incoming fault probability value (Pfi) of said j'th component is determined as: Pfi=1-(1-fp).sup.n where: n is the number of trials for a fault type of a component and is derived from said pre-determined test and quality information, fp is the fault probability and is derived from said pre-determined test and quality information.
Claim 49
Dependent Claim
36 words
The method of claim 43 wherein a yield (Y) is determined as: Y=Ycl+Yncl where: Ycl is a yield determined from clustered solder defects, and Yncl is a yield determined from non-clustered assembly defects and functional defects.
Claim 50
Dependent Claim
18 words
The method of claim 45 wherein said Ycl is determined as: ##EQU47## where: α is the clustering factor.
Claim 51
Dependent Claim
56 words
The method of claim 46 further comprising the step of: providing information relating to the assembly process used for said electronic assembly; estimating the clustering factor (α) as: ##EQU48## where: μ is the mean number of defects for said assembly process, and σ is the standard deviation of said number of defects for said assembly process.
Claim 52
Dependent Claim
12 words
The method of claim 45 wherein said Yncl is determined as: Yncl=e.sup.-Do
Claim 53
Dependent Claim
81 words
The method of claim 43: wherein said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly.
Claim 54
Dependent Claim
58 words
The method of claim 40 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect to a contribution of each component to said manufacturing test and quality attributes.
Claim 55
Dependent Claim
65 words
The method of claim 40 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
Claim 56
Dependent Claim
62 words
The method of claim 40 further comprising the steps of: performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
Claim 57
Independent Claim
97 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising: means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; means for providing information on a manufacturing test process; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes.
Claim 58
Independent Claim
97 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising: means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; means for providing information on a manufacturing test process; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes.
Claim 59
Independent Claim
253 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising: (a) means for providing information on the design of said electronic assembly; (b) means for providing pre-determined test and quality information relating to each component in said electronic assembly; (c) means for providing information on a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps; (d) means for estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps; (e) means for assigning the first of said sequential test steps as the current test step; (f) means for simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes; (g) means for determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of said stimulating means; (h) means for assigning the next of said sequential test steps as the current test step; and (i) means for activating said simulating means, said determining means, and said second assigning means for each of said plurality of test steps of said manufacturing test process.
Claim 60
Independent Claim
253 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising: (a) means for providing information on the design of said electronic assembly; (b) means for providing pre-determined test and quality information relating to each component in said electronic assembly; (c) means for providing information on a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps; (d) means for estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps; (e) means for assigning the first of said sequential test steps as the current test step; (f) means for simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes; (g) means for determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of said stimulating means; (h) means for assigning the next of said sequential test steps as the current test step; and (i) means for activating said simulating means, said determining means, and said second assigning means for each of said plurality of test steps of said manufacturing test process.
Claim 61
Independent Claim
96 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing test process, said system comprising: means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process.
Claim 62
Independent Claim
96 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing test process, said system comprising: means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process.
Claim 63
Independent Claim
104 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing assembly process, said system comprising: means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; means for providing information on a manufacturing test process; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process.
Claim 64
Independent Claim
104 words
A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing assembly process, said system comprising: means for providing information on the design of said electronic assembly; means for providing pre-determined test and quality information relating to each component in said electronic assembly; means for providing information on a manufacturing test process; and means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |