US5574853A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testing integrated circuit designs on a computer simulation using modified serialized scan patterns
Assignee: Texas Instruments Inc
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Filing: 1994-01-03
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Granted: 1996-11-12
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Expires: 2014-01-03
Abstract
Abstract A method to test an integrated circuit design on a computer simulation loads a desired simulation test vector in parallel into a scan chain (30). The simulation loads the desired vector at a slight offset or upstream shift allowing several serial shifts of the loaded vector through the scan chain (32). After the serial shifts, the initial IC state is set for executing an IC function (34). The IC function includes applying an input on the external pins and receiving an output from the external pins, given the initial IC state loaded by the simulation. After executing the IC function, the simulation unloads the resulting IC state in parallel (36) and compares the resulting IC state to a target vector (38).
Inventors
- 👤 Phillip T. Barch
- 👤 Christopher J. Ellingham
- 👤 Frederick L. Wagner
- 👤 John R. Larkin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:37
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318591
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
157 words
A method to test an integrated circuit design on a computer simulation, comprising the steps of; generating a desired vector comprising state data to be loaded into a serial scan chain of the integrated circuit design; loading the scan chain with the state data of the desired vector in parallel and offset by a predetermined number of shifts; shifting the state data by the predetermined number of shifts along the scan chain to position the state data in the scan chain, to set a desired state of the integrated circuit design; and executing a function of the integrated circuit design with the desired state wherein the step of generating a desired vector further comprises the steps of: generating a parallel data vector that represents the desired state of the integrated circuit design; and adjusting the parallel data vector to account for logical manipulations to the state data in the scan chain caused by the step of shifting.
Claim 2
Independent Claim
157 words
A method to test an integrated circuit design on a computer simulation, comprising the steps of; generating a desired vector comprising state data to be loaded into a serial scan chain of the integrated circuit design; loading the scan chain with the state data of the desired vector in parallel and offset by a predetermined number of shifts; shifting the state data by the predetermined number of shifts along the scan chain to position the state data in the scan chain, to set a desired state of the integrated circuit design; and executing a function of the integrated circuit design with the desired state wherein the step of generating a desired vector further comprises the steps of: generating a parallel data vector that represents the desired state of the integrated circuit design; and adjusting the parallel data vector to account for logical manipulations to the state data in the scan chain caused by the step of shifting.
Claim 3
Dependent Claim
162 words
A process for testing an integrated circuit, comprising the steps of: generating serialized scan patterns for testing the integrated circuit, the serialized scan patterns comprising state data to be loaded into a physical scan chain of the integrated circuit; generating, using the serialized scan patterns, simulation test vectors for testing a design of the integrated circuit on a computer simulation, the simulation test vectors comprising state data to be loaded into a simulated scan chain of the design of the integrated circuit; testing the design of the integrated circuit on the computer simulation by loading the simulated scan chain with the state data of the simulation test vectors using a parallel load followed by one or more shifts along the simulated scan chain; fabricating the integrated circuit to form a fabricated integrated circuit; and testing the fabricated integrated circuit by loading the physical scan chain with the state data of the serialized scan patterns using serial shifts along the physical scan chain.
Claim 4
Dependent Claim
162 words
A process for testing an integrated circuit, comprising the steps of: generating serialized scan patterns for testing the integrated circuit, the serialized scan patterns comprising state data to be loaded into a physical scan chain of the integrated circuit; generating, using the serialized scan patterns, simulation test vectors for testing a design of the integrated circuit on a computer simulation, the simulation test vectors comprising state data to be loaded into a simulated scan chain of the design of the integrated circuit; testing the design of the integrated circuit on the computer simulation by loading the simulated scan chain with the state data of the simulation test vectors using a parallel load followed by one or more shifts along the simulated scan chain; fabricating the integrated circuit to form a fabricated integrated circuit; and testing the fabricated integrated circuit by loading the physical scan chain with the state data of the serialized scan patterns using serial shifts along the physical scan chain.
Claim 5
Dependent Claim
19 words
The process of claim 2, and further comprising the step of designing the integrated circuit on a CAD/CAM system.
Claim 6
Dependent Claim
42 words
The process of claim 2, and further comprising the step of designing the integrated circuit on a CAD/CAM system, and wherein the steps of designing, testing the integrated circuit design, and fabricating are performed using a CAD/CAM model of the integrated circuit.
Claim 7
Dependent Claim
29 words
The process of claim 2, wherein the step of generating serialized scan patterns comprises generating serialized scan patterns from parallel test patterns generated on an automatic test pattern generator.
Claim 8
Dependent Claim
60 words
The process of claim 2, wherein the step of generating simulation test vectors further comprises the steps of: generating a parallel data vector that represents the desired state of the integrated circuit design; and adjusting the parallel data vector to account for logical manipulations to the state data caused by the one or more shifts along the simulated scan chain.
Claim 9
Dependent Claim
20 words
The process of claim 2, wherein the step of testing the integrated circuit design comprises voltage, temperature, and process testing.
Claim 10
Dependent Claim
34 words
The process of claim 2, wherein the step of testing the integrated circuit design validates both the functionality of the integrated circuit and the serialized scan patterns used to test the fabricated integrated circuit.
Claim 11
Dependent Claim
20 words
The process of claim 2, wherein the step of testing the integrated circuit design is performed on a hardware accelerator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |