Patent US5920575A successfully refreshed from Google Patents.
US5920575A
Expired / Lapsed
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VLSI test circuit apparatus and method
Assignee: International Business Machines Corp
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Filing: 1997-09-19
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Granted: 1999-07-06
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Expires: 2017-09-19
Abstract
Abstract An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2. The inputs to the multiplexer are functional data D, scan data I, and the control is scan enable SE. The L1 master latch receives its input from the output of the multiplexer and is clocked by the NAND of a -FLUSH (-A CLOCK) with an +EdgeClock (-C CLOCK.) The L2 slave latch receives its data input from the output of the L1 master latch and is clocked with the AND of -FREEZE (B CLOCK) and +EdgeClock. The output of the flip flop is the output of the L2 slave latch. This flip flop structure supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.
Inventors
- 👤 Roger Paul Gregor
- 👤 Steven Frederick Oakland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:23
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
86 words
A flip flop apparatus comprising: a multiplexer operable under control of a scan enable signal for generating from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch for generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; and a slave latch for generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal.
Claim 2
Dependent Claim
86 words
A flip flop apparatus comprising: a multiplexer operable under control of a scan enable signal for generating from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch for generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; and a slave latch for generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal.
Claim 3
Dependent Claim
156 words
A flip flop apparatus comprising: a multiplexer operable under control of a scan enable signal line for generating from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch including a first data input port, a first clock input port and a first output port, and responsive at said first data input port to said multiplexer output signal and at said first clock input port to the NAND of a flush signal with an edgeclock signal for generating a master latch output signal; and a slave latch including a second data input port, a second clock input port and a second output port, and responsive at said second data input port to said master latch output signal and at said second clock input port to at said second clock input port to the AND of a freeze signal and said edgeclock signal for generating a flip flop output signal.
Claim 4
Dependent Claim
156 words
A flip flop apparatus comprising: a multiplexer operable under control of a scan enable signal line for generating from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch including a first data input port, a first clock input port and a first output port, and responsive at said first data input port to said multiplexer output signal and at said first clock input port to the NAND of a flush signal with an edgeclock signal for generating a master latch output signal; and a slave latch including a second data input port, a second clock input port and a second output port, and responsive at said second data input port to said master latch output signal and at said second clock input port to at said second clock input port to the AND of a freeze signal and said edgeclock signal for generating a flip flop output signal.
Claim 5
Dependent Claim
74 words
A storage cell providing both MUX DFF and LSSD scan methodologies, comprising a first transmission gate at an input to said storage cell for receiving functional data; a second transmission gate at an input to said storage cell for receiving scan data; and a multiplexer for multiplexing said scan data and said functional data; whereby substantially no power dissipation is caused by scan data switching activity when functional data is enabled at said multiplexer.
Claim 6
Dependent Claim
74 words
A storage cell providing both MUX DFF and LSSD scan methodologies, comprising a first transmission gate at an input to said storage cell for receiving functional data; a second transmission gate at an input to said storage cell for receiving scan data; and a multiplexer for multiplexing said scan data and said functional data; whereby substantially no power dissipation is caused by scan data switching activity when functional data is enabled at said multiplexer.
Claim 7
Dependent Claim
63 words
The storage cell of claim 3, further comprising: a master latch for generating a master latch output signal from the output of said multiplexer and the NAND of a flush signal with an edgeclock signal; and a slave latch for generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal.
Claim 8
Dependent Claim
81 words
The flip flop apparatus of claim 1, further including a flush input, an edgeclock input, and a freeze input; said multiplexer including a functional data input port, a scan data input port and a scan enable control port; said master latch including a first data input port and a first clock input port and a master latch output port; and said slave latch including a second data input port and a second clock input port and a flip flop output port.
Claim 9
Dependent Claim
22 words
The flip flop apparatus of claim 5, selectively operable for performing edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.
Claim 10
Dependent Claim
70 words
The flip flop apparatus of claim 5, further comprising: a NAND gate for generating a NAND signal from said flush and said edgeclock inputs; an AND gate for generating an AND signal from said freeze and said edgeclock inputs; and said flip flop apparatus being operable responsive to said flush input and said freeze input being held to logical 1 for performing edge sensitive operations clocked by said edgeclock input.
Claim 11
Dependent Claim
145 words
The flip flop apparatus of claim 7, further comprising: said multiplexer responsive to a scan enable signal at said scan enable input port for passing scan data to said master latch and responsive to a not scan enable signal at said scan enable input port for passing functional data to said master latch; said master latch being responsive to said NAND signal being logical 1 for accepting data from said multiplexer and said slave latch being responsive to said AND signal being logical 0 for holding state; and said master latch being responsive to said NAND signal being logical 0 for holding state and said slave latch being responsive to said AND signal being logical 1 for propagating data stored in said master latch to said flip flop output port; whereby a single clock, the edgeclock, is used to clock data through said flip flop.
Claim 12
Dependent Claim
128 words
A flip flop for performing edge sensitive operations, comprising: a multiplexer operable under control of a scan enable signal for generating selectively from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch for generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; a slave latch for generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal; and said edgeclock signal operable when said flush signal and said freeze signal are both logical 1 for clocking data from said multiplexer through said master latch and said slave latch to the output of said flip flop.
Claim 13
Dependent Claim
128 words
A flip flop for performing edge sensitive operations, comprising: a multiplexer operable under control of a scan enable signal for generating selectively from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch for generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; a slave latch for generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal; and said edgeclock signal operable when said flush signal and said freeze signal are both logical 1 for clocking data from said multiplexer through said master latch and said slave latch to the output of said flip flop.
Claim 14
Dependent Claim
23 words
The flip flop of claim 9 further operable responsive to said scan enable signal being held to logic 0 for performing functional operations.
Claim 15
Dependent Claim
23 words
The flip flop of claim 9 further operable responsive to said scan enable signal being held to logic 1 for performing scan operations.
Claim 16
Dependent Claim
45 words
The flip flop of claim 9 further operable responsive to said freeze signal being held to logic 0 for performing freeze operations, whereby said slave latch is held frozen in state to reduce power by preventing switching activity in logic fed by said slave latch.
Claim 17
Dependent Claim
69 words
The flip flop of claim 9 further operable responsive to said flush signal being held at logic 0 while said freeze signal and said edgeclock signals are held at logic 1 for performing flush operations, whereby responsive to said scan enable being logical 1 scan data is flushed through said flip flop and responsive to said scan enable being logical 0 functional data is flushed through said flip flop.
Claim 18
Dependent Claim
164 words
The flip flop of claim 9 further operable for performing test operations including scan data pass mode responsive to said scan enable and said edgeclock signals being held to logic 1 to enable said multiplexer to pass scan data and said flush and freeze signals to act as level sensitive clocks; disabled mode disabling both said master latch said slave latch from accepting new data responsive to said freeze signal being held to logical 0 and said flush signal being held to logical 1; scanning mode responsive to alternatively pulsing said flush signal to logical 0 while holding said freeze signal to logical 0 and then pulsing said freeze signal to logical 1 while holding said flush signal to logic 1 to enable said slave latch to pass master data to said slave latch output; and flush mode by holding said flush signal to logic 0 and said freeze signal to logic 1 to simultaneously enable both said master latch and said slave latch.
Claim 19
Dependent Claim
133 words
A flip flop for performing level sensitive functional operations, comprising: a multiplexer operable under control of a scan enable signal for generating selectively from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch for generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; a slave latch for generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal; and said edgeclock signal being held to logic 1 such that said freeze signal and said flush signal operate as a pair of level sensitive clocks and said master latch and said slave latch operate as a pair of level sensitive latches.
Claim 20
Dependent Claim
133 words
A flip flop for performing level sensitive functional operations, comprising: a multiplexer operable under control of a scan enable signal for generating selectively from functional data and scan data inputs to said flip flop a multiplexer output signal; a master latch for generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; a slave latch for generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal; and said edgeclock signal being held to logic 1 such that said freeze signal and said flush signal operate as a pair of level sensitive clocks and said master latch and said slave latch operate as a pair of level sensitive latches.
Claim 21
Independent Claim
79 words
A method for operating a flip flop, comprising the steps of: generating responsive to a scan enable signal from functional data and scan data inputs to said flip flop a multiplexer output signal; generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; and generating a slave latch output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal.
Claim 22
Independent Claim
79 words
A method for operating a flip flop, comprising the steps of: generating responsive to a scan enable signal from functional data and scan data inputs to said flip flop a multiplexer output signal; generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; and generating a slave latch output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal.
Claim 23
Dependent Claim
122 words
The method of claim 16, further for performing edge sensitive operations comprising the steps of: generating under control of a scan enable signal selectively from functional data and scan data inputs to said flip flop a multiplexer output signal; generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; generating a flip flop output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal; and clocking data responsive to said edgeclock signal from said multiplexer through said master latch and said slave latch to the output of said flip flop when said flush signal and said freeze signal are both logical 1.
Claim 24
Dependent Claim
24 words
The method of claim 17 comprising the further step of performing functional operations responsive to said scan enable signal being held to logic 0.
Claim 25
Dependent Claim
24 words
The method of claim 17 comprising the further step of performing scan operations responsive to said scan enable signal being held to logic 1.
Claim 26
Dependent Claim
38 words
The method of claim 17 comprising the further step of performing freeze operations responsive to said freeze signal being held to logic 0, whereby power is reduced by preventing switching activity in logic fed by said flip flop.
Claim 27
Dependent Claim
70 words
The method of claim 17 comprising the further step of performing flush operations responsive to said flush signal being held at logic 0 while said freeze signal and said edgeclock signals are held at logic 1, whereby responsive to said scan enable being logical 1 scan data is flushed through said flip flop and responsive to said scan enable being logical 0 functional data is flushed through said flip flop.
Claim 28
Independent Claim
125 words
A method for operating a flip flop for performing level sensitive functional operations, comprising the steps of: generating responsive to a scan enable signal from functional data and scan data inputs to said flip flop a multiplexer output signal; generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; generating a slave latch output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal; responsive to said edgeclock signal being held to logic 1, operating said freeze signal and said flush signal as a pair of level sensitive clocks and said master latch and said slave latch operate as a pair of level sensitive latches.
Claim 29
Independent Claim
125 words
A method for operating a flip flop for performing level sensitive functional operations, comprising the steps of: generating responsive to a scan enable signal from functional data and scan data inputs to said flip flop a multiplexer output signal; generating a master latch output signal from said multiplexer output signal and the NAND of a flush signal with an edgeclock signal; generating a slave latch output signal from said master latch output signal and the AND of a freeze signal and said edgeclock signal; responsive to said edgeclock signal being held to logic 1, operating said freeze signal and said flush signal as a pair of level sensitive clocks and said master latch and said slave latch operate as a pair of level sensitive latches.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-05 | 2003-01-04 | 2003-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-05 | 2007-01-04 | 2007-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-05 | 2011-01-04 | 2011-07-06 | $7700.00 | Window Closed / Lapsed |