Register stage having at least two memory stages for coordinating disparate clock signals for use in boundary scan

Claim 2

An integrated circuit comprising a plurality of clocked register stages, each register stage comprising a respective series arrangement of first and second memory stages, the first memory stage being one of an edge-triggered memory stage and a level-triggered memory stage, and the second of the memory stages being the other of the edge and level triggered memory stages each of the first and second memory stages having at least one respective clock input, a respective data input, and a respective data output, a respective first multiplexer preceding the data input of the first memory stage, the respective first multiplexer having a respective select input, at least first and second respective data inputs, and a respective data output, wherein during testing of the integrated circuit the edge-triggered memory stages of the register stages receive a same first clock signal on their respective clock inputs, and the level-clocked memory stages of the register stages receive a same second clock signal, the first and second clock signals having non-overlapping pulses, and for loading and reading-out test signal patterns, each first multiplexer receives a first select signal on the respective select input in order to connect one of the respective data inputs for test signals to the respective data output, and in normal operation, a first signal value is constantly applied to the respective clock input of each level-triggered memory stage of the register stages to switch said level-triggered memory stage to transparent operation.

Claim 3

An integrated circuit comprising a plurality of clocked register stages, each register stage comprising a respective series arrangement of first and second level-triggered memory stages, each stage having at least one respective clock input, a respective data input, and a respective output, a respective first multiplexer, preceding the respective data input of the first memory stage of the series arrangement, having a respective select input, at least two respective data inputs, and a respective data output, and a respective second multiplexer, preceding the respective clock input of the second memory stage, having a respective select input, at least two respective data inputs, and a respective data output, wherein during testing of the integrated circuit, the first memory stages receive a same first clock signal on their respective clock inputs, the second multiplexers receive a same second clock signal on a first respective one of the respective clock inputs, the first and second clock signals having non-overlapping pulses, and for loading and reading-out test signal patterns, at least one of the first multiplexers receives a first select signal on its respective select input in order to connect a data input for test signals to the respective data output, and at least one of the second multiplexers receives a second select signal on its respective select input, in order to connect the first clock input to its clock output, and in normal operation, the second multiplexers receive the inverse of the first clock signal on a respective second clock input and the inverse of the second select signal on the respective select inputs in order to connect the second clock input to the respective clock outputs.

Claim 4

An integrated circuit comprising a plurality of clocked register stages, each register stage comprising a respective series arrangement of first and second level-triggered memory stages, each stage having at least one respective clock input, a respective data input, and a respective output, a respective first multiplexer, preceding the respective data input of the first memory stage of the series arrangement, having a respective select input, at least two respective data inputs, and a respective data output, and a respective second multiplexer, preceding the respective clock input of the second memory stage, having a respective select input, at least two respective data inputs, and a respective data output, wherein during testing of the integrated circuit, the first memory stages receive a same first clock signal on their respective clock inputs, the second multiplexers receive a same second clock signal on a first respective one of the respective clock inputs, the first and second clock signals having non-overlapping pulses, and for loading and reading-out test signal patterns, at least one of the first multiplexers receives a first select signal on its respective select input in order to connect a data input for test signals to the respective data output, and at least one of the second multiplexers receives a second select signal on its respective select input, in order to connect the first clock input to its clock output, and in normal operation, the second multiplexers receive the inverse of the first clock signal on a respective second clock input and the inverse of the second select signal on the respective select inputs in order to connect the second clock input to the respective clock outputs.

Claim 5

An integrated circuit comprising a plurality of clocked register stages each register stage comprising a respective series arrangement of first and second level-triggered memory stages each having at least one respective clock input, a respective data input, and a respective output, a respective third similar memory stage, a respective first multiplexer, preceding a data input of the third memory stage, having a respective select input, at least two respective data inputs, and a respective data output, of which a first data input is connected to the respective data input of the respective first memory stage, a respective second multiplexer having a respective select input, first and second respective data inputs, connected to the respective outputs of the respective first and third memory stage, respectively, and a respective data output connected to the respective data input of the respective second memory stage, wherein during testing of the integrated circuit the second memory stages of the register stages receive a same first clock signal on the respective clock inputs, and the third memory stages of the register stages receive a same second clock signal on the respective clock inputs, the first and second clock signals having non-overlapping pulses, and for loading and reading-out test signal patterns, the first and the second multiplexers receive a similar first select signal on the respective select input, in order to couple a data input for tests signals to the respective data input of the third memory stage, and the respective output of the third memory stage to the respective data input of the second memory stage, and for loading test results, the first select signal is inverted at least for a pulse duration of the second clock signal and is not inverted at least for a pulse duration of the first clock signal, and in normal operation the first memory stages receive an inverted version of the first clock signal on their respective clock inputs and the second multiplexers receive an inverted version of the select signal, in order to couple the respective outputs of the first memory stages to the respective data inputs of the second memory stages.

Claim 6

An integrated circuit comprising a plurality of clocked register stages each register stage comprising a respective series arrangement of first and second level-triggered memory stages each having at least one respective clock input, a respective data input, and a respective output, a respective third similar memory stage, a respective first multiplexer, preceding a data input of the third memory stage, having a respective select input, at least two respective data inputs, and a respective data output, of which a first data input is connected to the respective data input of the respective first memory stage, a respective second multiplexer having a respective select input, first and second respective data inputs, connected to the respective outputs of the respective first and third memory stage, respectively, and a respective data output connected to the respective data input of the respective second memory stage, wherein during testing of the integrated circuit the second memory stages of the register stages receive a same first clock signal on the respective clock inputs, and the third memory stages of the register stages receive a same second clock signal on the respective clock inputs, the first and second clock signals having non-overlapping pulses, and for loading and reading-out test signal patterns, the first and the second multiplexers receive a similar first select signal on the respective select input, in order to couple a data input for tests signals to the respective data input of the third memory stage, and the respective output of the third memory stage to the respective data input of the second memory stage, and for loading test results, the first select signal is inverted at least for a pulse duration of the second clock signal and is not inverted at least for a pulse duration of the first clock signal, and in normal operation the first memory stages receive an inverted version of the first clock signal on their respective clock inputs and the second multiplexers receive an inverted version of the select signal, in order to couple the respective outputs of the first memory stages to the respective data inputs of the second memory stages.

Claim 7

An integrated circuit as claimed in claim 1, wherein each level-triggered memory stage comprises a series arrangement of: a respective second multiplexer, including a respective control input connected to a clock input, and a first input connected to a data input; and respective first and second inverters, a respective output of the second inverter being connected to a second input of the respective second multiplexer a respective input of the first inverter being connected to an output of the respective second multiplexer.

Claim 8

An integrated circuit as claimed in claim 2, wherein each level-triggered memory stage comprises a series arrangement of: a respective third multiplexer, including a respective control input connected to a clock input, and a first input connected to a data input; and respective first and second inverters, a respective output of the second inverter being connected to a second input of the respective third multiplexer a respective input of the first inverter being connected to an output of the respective third multiplexer.

Claim 9

An integrated circuit as claimed in claim 3, wherein each level-triggered memory stage comprises a series arrangement of: a respective third multiplexer, including a respective control input connected to a clock input, and a first input connected to a data input; and respective first and second inverters, a respective output of the second inverter being connected to a second input of the respective third multiplexer a respective input of the first inverter being connected to an output of the respective third multiplexer.