US5150366A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reduced delay circuits for shift register latch scan strings
Assignee: International Business Machines Corp
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Filing: 1990-08-01
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Granted: 1992-09-22
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Expires: 2010-08-01
Abstract
Abstract Delays in critical signal paths are eliminated in circuits employing level sensitive scan design methods for implementing self-test operations. In particular, scan strings associataed with primary input lines are segregated and supplied to a separate distinct signature register so as to permit simplified degating circuitry on the input side of those shift register latches which are in fact associated with primary input signal lines.
Inventors
- 👤 Paul H. Bardell, Jr.
- 👤 William H. McAnney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
151 words
An apparatus for the built-in self testing of sequential digital logic circuits, said apparatus comprising: means for generating pseudo-random bit sequences on a plurality of output signal lines; a first set of shift register latches comprising at least one scan string coupled to said output signal lines of said sequence generating means; a second set of shift register latches comprising at least one scan string distinct from any string in said first set of shift register latches, with at least one scan string from said second set also being coupled to said output signal lines of said sequence generating means; a first register coupled so as to receive output bit sequences from at least one scan string from said first set of shift register latches; and a second register coupled so as to receive output bit sequences from at least one scan string from said second set of shift register latches.
Claim 2
Independent Claim
151 words
An apparatus for the built-in self testing of sequential digital logic circuits, said apparatus comprising: means for generating pseudo-random bit sequences on a plurality of output signal lines; a first set of shift register latches comprising at least one scan string coupled to said output signal lines of said sequence generating means; a second set of shift register latches comprising at least one scan string distinct from any string in said first set of shift register latches, with at least one scan string from said second set also being coupled to said output signal lines of said sequence generating means; a first register coupled so as to receive output bit sequences from at least one scan string from said first set of shift register latches; and a second register coupled so as to receive output bit sequences from at least one scan string from said second set of shift register latches.
Claim 3
Dependent Claim
24 words
The apparatus of claim 1 in which said first set of shift register latches comprises memory elements receiving primary inputs to said sequential circuit.
Claim 4
Dependent Claim
22 words
The apparatus of claim 1 in which said first set of shift register latches are arranged in a plurality of scan strings.
Claim 5
Dependent Claim
22 words
The apparatus of claim 1 in which said second set of shift register latches are arranged in a plurality of scan strings.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-22 | 1996-03-23 | 1996-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-22 | 2000-03-23 | 2000-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-22 | 2004-03-23 | 2004-09-22 | $7700.00 | Window Closed / Lapsed |