LSI logic circuit

Claim 2

A logic circuit comprising: a first terminal; a second terminal; a plurality of combinational circuits disposed between the first and second terminals; and a plurality of flip-flops with at least one flip-flop being coupled to each of said combinational circuits, said plurality of flip-flops being coupled between said first and second terminals for shifting test data which is inputted to the flip-flop coupled to said first terminal through the coupled flip-flops to the second terminal, each flip-flop having a switching means coupled thereto which receives a control signal and which inhibits reception of a normal mode clock in response to said control signal during a period when said test data is inputted thereto.

Claim 3

A logic circuit in accordance with claim 1 wherein: the first and second terminals are external terminals.

Claim 4

A logic circuit according to claim 2 wherein: said master latch circuit is coupled to receive a first clock signal for controlling latching of said test data; said slave latch is coupled to receive a second clock signal for controlling latching of said test data outputted from said master latch circuit; and wherein levels of said first and second clock signals are alternately raised to high levels.

Claim 5

A logic circuit according to claim 1 wherein: each flip-flop includes a master latch circuit coupled in series with a slave latch circuit.

Claim 6

A logic circuit in accordance with claim 1 wherein: the first and second terminals are external terminals.

Claim 7

A logic circuit comprising: a first terminal; a second terminal; a plurality of combinational circuits; and a plurality of latch means coupled to said combinational circuits, said plurality of latch means being coupled between said first and second terminals for shifting test data which is inputted to the latch means coupled to said first terminal through the coupled latch means to said second terminal; and at least one of the latch means includes an input terminal coupled to receive an output signal provided from a combinational circuit, a clock signal input terminal supplied with a clock signal for controlling latching of said output signal therein and means, responsive to a control signal, for invalidating said output signal and said clock signal during the test mode.

Claim 8

A logic circuit comprising: a first terminal; a second terminal; a plurality of combinational circuits; and a plurality of latch means coupled to said combinational circuits, said plurality of latch means being coupled between said first and second terminals for shifting test data which is inputted to the latch means coupled to said first terminal through the coupled latch means to said second terminal; and at least one of the latch means includes an input terminal coupled to receive an output signal provided from a combinational circuit, a clock signal input terminal supplied with a clock signal for controlling latching of said output signal therein and means, responsive to a control signal, for invalidating said output signal and said clock signal during the test mode.

Claim 9

A logic circuit in accordance with claim 6 wherein: the first and second terminals are external terminals.

Claim 10

A logic circuit according to claim 7, wherein: each of said first and second latch circuit is comprised of a master and a slave latch circuit.

Claim 11

A logic circuit according to claim 6, wherein: each of said plurality of latch means includes a master latch and a slave latch.

Claim 12

A logic circuit implemented in a single semiconductor chip, comprising: a first terminal; a second terminal; first and second combinational circuits; a first latch circuit having an input terminal coupled to an output of said first combinational circuit for receiving normal data or test mode data from said first combinational circuit, and an output terminal coupled to an input of said second combinational circuit; a second latch circuit having an input terminal for receiving normal data or test mode data from an output said second combinational circuit and an output terminal coupled to said second terminal; and wherein each of said first and second latch circuits further includes a clock signal input terminal supplied with a clock signal for controlling latching of normal data provided to the input terminal and means, responsive to a mode control signal, for invalidating the clock signal and the output signal when said mode control signal indicates a test mode; and said latch circuits functioning to shift test data between the first and second terminals.

Claim 13

A logic circuit implemented in a single semiconductor chip, comprising: a first terminal; a second terminal; first and second combinational circuits; a first latch circuit having an input terminal coupled to an output of said first combinational circuit for receiving normal data or test mode data from said first combinational circuit, and an output terminal coupled to an input of said second combinational circuit; a second latch circuit having an input terminal for receiving normal data or test mode data from an output said second combinational circuit and an output terminal coupled to said second terminal; and wherein each of said first and second latch circuits further includes a clock signal input terminal supplied with a clock signal for controlling latching of normal data provided to the input terminal and means, responsive to a mode control signal, for invalidating the clock signal and the output signal when said mode control signal indicates a test mode; and said latch circuits functioning to shift test data between the first and second terminals.

Claim 14

A logic circuit implemented in a single semiconductor chip comprising: a plurality of combinational circuits; a first terminal; a second terminal; a plurality of latch circuits coupled to said combinational circuits, said plurality of latch circuits being coupled between said first and second terminals; each latch circuit including a master flip-flop circuit, a slave flip-flop circuit having an input coupled to an output of said master flip-flop circuit, an input terminal for receiving output data generated by one of the combinational circuits, a normal mode clock signal input terminal for receiving a first clock signal for controlling latching of said output data in said master flip-flop circuit, a test data input terminal for receiving test data, a test mode clock signal input terminal, coupled to said master flip-flop circuit, for controlling latching of said test data in said master flip-flop circuit; switching means disposed between said master flip-flop circuit and said input terminal and said normal mode clock signal input terminal; a mode control signal input terminal for receiving a control signal for controlling operation of said switching means; and wherein said switching means is in an off state when said control signal indicates a test mode.

Claim 15

A logic circuit implemented in a single semiconductor chip comprising: a plurality of combinational circuits; a first terminal; a second terminal; a plurality of latch circuits coupled to said combinational circuits, said plurality of latch circuits being coupled between said first and second terminals; each latch circuit including a master flip-flop circuit, a slave flip-flop circuit having an input coupled to an output of said master flip-flop circuit, an input terminal for receiving output data generated by one of the combinational circuits, a normal mode clock signal input terminal for receiving a first clock signal for controlling latching of said output data in said master flip-flop circuit, a test data input terminal for receiving test data, a test mode clock signal input terminal, coupled to said master flip-flop circuit, for controlling latching of said test data in said master flip-flop circuit; switching means disposed between said master flip-flop circuit and said input terminal and said normal mode clock signal input terminal; a mode control signal input terminal for receiving a control signal for controlling operation of said switching means; and wherein said switching means is in an off state when said control signal indicates a test mode.

Claim 16

A logic circuit in accordance with claim 11 wherein: the first and second terminals are external terminals.

Claim 17

A logic circuit according to claim 11, wherein: each latch circuit further includes another clock input terminal coupled to said slave flip-flop.