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EP0173945A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Integrated circuit device

Assignee: Hitachi Ltd
•
Filing: 1985-08-27
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Granted: —
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Expires: 2005-08-27
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Abstract

Abstract An integrated circuit device comprises combinational circuits and sequential circuits; the sequential circuits each is provided with a (common) input control signal terminal (16) for controlling the permission to input main input terminal signals into the sequential circuit, a test data input/output terminal (17-1,17-2), a read/write signal terminal (8-1,8-2,8-3,9-1,9-2,9-3) for controlling the transfer of the test data, and a latch circuit. The integrated circuit device is partitioned into sequential circuits groups (1',2',3'), and combinational circuit groups (4,5,6) used as partitioning test units, the main input-output terminal groups of which are connected with the sequential circuits groups through wiring layers (11,13,15), test data are written and read out, from and to the sequential circuits groups under control of read/write signal lines through bus lines (17-1,17-2) dedicated to testing. Thus, a higher fault-coverage ratio can be easily obtained with smaller number of steps and small test circuits areas.

Inventors

  • 👤 Shigeo Kuboki
  • 👤 Ikuro Masuda
  • 👤 Toshiaki Masuda
  • 👤 Terumine Hayashi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 05:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G11; G11C; G11C7/00; G11C7/10; G11C7/1051

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 144 words
An integrated circuit device comprising combinational circuits and sequential circuits, said sequential circuits each provided with a common input control signal terminal (16) for controlling the permission to input main input terminal (10, 12, 14) signals, a test data input/output terminal (17-1, 17-2), a read/write signal terminals (8-1, 8-2, 8-3, 9-1, 9-2, 9-3) for controlling the transfer of the test data, and a latch circuit, said integrated circuit device partitioned into sequential circuits groups (1', 2', 3') and combinational circuits groups (4, 5, 6) used as partitioning test units, the main input/output terminal groups of which are connected with the sequential circuit groups through wiring layers (11, 13, 15), respectively, test data are written and read out, to and from said sequential circuit perform a read/write operation of the diagnosis under control of read/write terminal signals through bus lines (17-1, 17-2) dedicated to testing.
Claim 2
Dependent Claim 144 words
An integrated circuit device comprising combinational circuits and sequential circuits, said sequential circuits each provided with a common input control signal terminal (16) for controlling the permission to input main input terminal (10, 12, 14) signals, a test data input/output terminal (17-1, 17-2), a read/write signal terminals (8-1, 8-2, 8-3, 9-1, 9-2, 9-3) for controlling the transfer of the test data, and a latch circuit, said integrated circuit device partitioned into sequential circuits groups (1', 2', 3') and combinational circuits groups (4, 5, 6) used as partitioning test units, the main input/output terminal groups of which are connected with the sequential circuit groups through wiring layers (11, 13, 15), respectively, test data are written and read out, to and from said sequential circuit perform a read/write operation of the diagnosis under control of read/write terminal signals through bus lines (17-1, 17-2) dedicated to testing.
Claim 3
Dependent Claim 45 words
An integrated circuit device according to Claim 1, wherein said input control signal terminals (16) of said sequential circuits (1', 2', 3') are connected in common, and latch timing signal terminals (30) of said sequential circuits used for the latch function are connected in common.

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