System and method for equalizing data buffer storage and fetch rates of peripheral devices

Claim 2

A computer system, comprising: a data buffer configured to store data, wherein a fraction of the data buffer contains unread data; a central processing unit (CPU) operably coupled to the data buffer and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction; a first peripheral device operably coupled to the data buffer and to the CPU, wherein the first peripheral device is configured to produce a plurality of data prior to storing the plurality of data within the data buffer, and wherein the first peripheral device comprises a reload register, and wherein the rate at which the first peripheral device stores the data within the data buffer is dependent upon the contents of the reload register, and wherein the first peripheral device is configured to receive the reload value and to store the reload value within the reload register; a second peripheral device operably coupled to the data buffer, wherein the second peripheral device is configured to fetch the data from the data buffer; wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

Claim 3

The computer system as recited in claim 1, wherein the CPU produces the reload value such that the rate at which the first peripheral device stores the data within the data buffer is substantially equal to the rate at which the second peripheral device fetches the data from the data buffer.

Claim 4

The computer system as recited in claim 1, wherein the fraction of the data buffer containing unread data is the number of memory locations between the adjusted write pointer and the read pointer.

Claim 5

The computer system as recited in claim 1, wherein the data buffer comprises a portion of a system memory operably coupled to the CPU.

Claim 6

The computer system as recited in claim 1, wherein the first peripheral device is an audio signal processor, and wherein the second peripheral device is an audio device configured to drive a speaker.

Claim 7

A computer system, comprising: a system memory configured to store data and comprising a data buffer, wherein a fraction of the data buffer contains unread data; an expansion bus adapted for coupling to one or more peripheral devices; a bus bridge coupled between the system memory and the expansion bus; a central processing unit (CPU) coupled to the bus bridge and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction; a first peripheral device coupled to the expansion bus, wherein the first peripheral device is configured to produce a plurality of data prior to storing the plurality of data within the data buffer, and wherein the first peripheral device comprises a reload register, and wherein the rate at which the first peripheral device stores the data within the data buffer is dependent upon the contents of the reload register, and wherein the first peripheral device is configured to receive the reload value and to store the reload value within the reload register; a second peripheral device coupled to the bus bridge, wherein the second peripheral device is configured to fetch the data from the data buffer; wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

Claim 8

A computer system, comprising: a system memory configured to store data and comprising a data buffer, wherein a fraction of the data buffer contains unread data; an expansion bus adapted for coupling to one or more peripheral devices; a bus bridge coupled between the system memory and the expansion bus; a central processing unit (CPU) coupled to the bus bridge and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction; a first peripheral device coupled to the expansion bus, wherein the first peripheral device is configured to produce a plurality of data prior to storing the plurality of data within the data buffer, and wherein the first peripheral device comprises a reload register, and wherein the rate at which the first peripheral device stores the data within the data buffer is dependent upon the contents of the reload register, and wherein the first peripheral device is configured to receive the reload value and to store the reload value within the reload register; a second peripheral device coupled to the bus bridge, wherein the second peripheral device is configured to fetch the data from the data buffer; wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

Claim 9

The computer system as recited in claim 6, wherein the CPU produces the reload value such that the rate at which the first peripheral device stores the data within the data buffer is substantially equal to the rate at which the second peripheral device fetches the data from the data buffer.

Claim 10

The computer system as recited in claim 6, wherein the fraction of the data buffer containing unread data is the number of memory locations between the adjusted write pointer and the read pointer.

Claim 11

The computer system as recited in claim 6, wherein the data comprises audio data, and wherein the first peripheral device comprises: a divider circuit comprising the reload register, wherein the divider circuit is configured to produce a frame batch clock signal having a period dependent upon the contents of the reload register; and a signal processor coupled to receive the frame batch clock signal and configured to produce the audio data, wherein the signal processor initiates processing of a predetermined number of audio signal samples in response to the frame batch clock signal.

Claim 12

The computer system as recited in claim 6, wherein the first peripheral device is an audio signal processor, and wherein the second peripheral device is an audio device configured to drive a speaker.

Claim 13

A computer system, comprising: a system memory configured to store data and comprising a data buffer, wherein a fraction of the data buffer contains unread data; an expansion bus adapted for coupling to one or more peripheral devices; a bus bridge coupled between the system memory and the expansion bus; a central processing unit (CPU) coupled to the bus bridge and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction; a first peripheral device coupled to the expansion bus, wherein the first peripheral device is configured to produce a plurality of audio data prior to storing the plurality of audio data within the data buffer, and wherein the first peripheral device comprises: a divider circuit comprising: a reload register; and a counter coupled to the reload register and coupled to receive a master clock signal having a predetermined period, wherein the divider circuit is configured to produce a frame batch clock signal in response to the master clock signal and having a period dependent upon the contents of the reload register; and a signal processor coupled to receive the frame batch clock signal and configured to produce the plurality of audio data, wherein the signal processor initiates processing of a predetermined number of audio signal samples in response to the frame batch clock signal; a second peripheral device coupled to the bus bridge, wherein the second peripheral device is configured to fetch the data from the data buffer; wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

Claim 14

A computer system, comprising: a system memory configured to store data and comprising a data buffer, wherein a fraction of the data buffer contains unread data; an expansion bus adapted for coupling to one or more peripheral devices; a bus bridge coupled between the system memory and the expansion bus; a central processing unit (CPU) coupled to the bus bridge and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction; a first peripheral device coupled to the expansion bus, wherein the first peripheral device is configured to produce a plurality of audio data prior to storing the plurality of audio data within the data buffer, and wherein the first peripheral device comprises: a divider circuit comprising: a reload register; and a counter coupled to the reload register and coupled to receive a master clock signal having a predetermined period, wherein the divider circuit is configured to produce a frame batch clock signal in response to the master clock signal and having a period dependent upon the contents of the reload register; and a signal processor coupled to receive the frame batch clock signal and configured to produce the plurality of audio data, wherein the signal processor initiates processing of a predetermined number of audio signal samples in response to the frame batch clock signal; a second peripheral device coupled to the bus bridge, wherein the second peripheral device is configured to fetch the data from the data buffer; wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

Claim 15

The computer system as recited in claim 11, wherein the first peripheral device is configured to receive the reload value and to store the reload value within the reload register.

Claim 16

The computer system as recited in claim 11, wherein the counter produces a plurality of binary output signals representing a binary value, and wherein the binary value is decremented during each cycle of the master clock signal, and wherein when the binary values of all counter output signals are 0, the counter outputs are set to the corresponding values stored within the reload register.

Claim 17

The computer system as recited in claim 13, wherein the frame batch clock signal is the value of the most significant binary output signal produced by the counter.

Claim 18

The computer system as recited in claim 11, wherein the fraction of the data buffer containing unread data is the number of memory locations between the adjusted write pointer and the read pointer.

Claim 21

The method as recited in claim 16, wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer.

Claim 22

The method as recited in claim 16, wherein the rate at which the first peripheral device stores the data within the data buffer is dependent upon the contents of the reload register.

Claim 23

The method as recited in claim 16, wherein the reload value delta is 0 when the number of memory locations between the adjusted write pointer and the read pointer is approximately equal to half of the total number of memory locations within the data buffer.

Claim 24

The method as recited in claim 16, wherein the reload value delta is positive when the number of memory locations between the adjusted write pointer and the read pointer is substantially greater than half of the total number of memory locations within the data buffer.

Claim 25

The method as recited in claim 16, wherein the reload value delta is negative when the number of memory locations between the adjusted write pointer and the read pointer is substantially less than half of the total number of memory locations within the data buffer.