Patent US5671019A successfully refreshed from Google Patents.
US4464772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency synthesizer for providing a pseudo-constant frequency signal
Assignee: EMC Corp
•
Filing: 1980-02-11
•
Granted: 1984-08-07
•
Expires: 2000-02-11
Abstract
Abstract A unique frequency synthesizer unit for use in a data processing system I/O interface unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics.
Inventors
- 👤 Edward M. Buckley
- 👤 Michael B. Druke
- 👤 Roger W. March
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:08
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667; G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/38; G06F13/42; G06F9/00; G06F9/06; G06F9/22; G06F9/26
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
302 words
A frequency synthesizer for providing an output signal having the same pseudo-constant frequency with a known period in response to a selected one of a plurality of input signals each having a different fixed frequency, the frequencies of said plurality of input signals being of the same order of magnitude as, or higher than, said pseudo-constant frequency, said frequency synthesizer comprising: decode means responsive to a coded signal representing a selected one of said plurality of input signals for providing a control signal corresponding to said selected input signal; first means responsive to said control signal for supplying a number representing a selected number of successive sub-groups of one or more cycles of said selected input signal, the number of cycles of said input signal in each said sub-group being one of two consecutive integers identifiable as a high integer and a low integer; counter means responsive to said selected number and to said output signal for providing a position count signal at each successive sub-group; parsing means responsive to said position count signal and to said control signal for providing a high/low signal specifying the sub-group position at which a high integer number of input cycles are used or a low integer number of input cycles are used; and second means responsive to said selected one of said input signals, to said control signal, and to said high/low signal for specifying said high integer and said low integer and for supplying an output cycle at each successive high or low sub-group of input cycles, said output cycles forming said output signal having said pseudo-constant frequency, the order in which said high and low sub-groups occur being selected to maintain any error in said output signal at a value less than or equal to the cycle time of said selected input signal.
Claim 2
Dependent Claim
302 words
A frequency synthesizer for providing an output signal having the same pseudo-constant frequency with a known period in response to a selected one of a plurality of input signals each having a different fixed frequency, the frequencies of said plurality of input signals being of the same order of magnitude as, or higher than, said pseudo-constant frequency, said frequency synthesizer comprising: decode means responsive to a coded signal representing a selected one of said plurality of input signals for providing a control signal corresponding to said selected input signal; first means responsive to said control signal for supplying a number representing a selected number of successive sub-groups of one or more cycles of said selected input signal, the number of cycles of said input signal in each said sub-group being one of two consecutive integers identifiable as a high integer and a low integer; counter means responsive to said selected number and to said output signal for providing a position count signal at each successive sub-group; parsing means responsive to said position count signal and to said control signal for providing a high/low signal specifying the sub-group position at which a high integer number of input cycles are used or a low integer number of input cycles are used; and second means responsive to said selected one of said input signals, to said control signal, and to said high/low signal for specifying said high integer and said low integer and for supplying an output cycle at each successive high or low sub-group of input cycles, said output cycles forming said output signal having said pseudo-constant frequency, the order in which said high and low sub-groups occur being selected to maintain any error in said output signal at a value less than or equal to the cycle time of said selected input signal.
Claim 3
Dependent Claim
64 words
A frequency synthesizer in accordance with claim 1 wherein said second means includes: integer selection means responsive to said high/low signal and to said control signal for providing further coded signals representing said high and low integers as said successive sub-groups; and output means responsive to said further coded signals and to said selected one of said input signals for supplying said output signal.
Claim 4
Dependent Claim
22 words
A frequency synthesizer in accordance with claim 2 wherein said parsing means is a read-only-memory, said integer selection means is a read-only-memory.
Claim 5
Dependent Claim
198 words
A frequency synthesizer responsive to a selected one of a plurality of input signals having a first frequency for providing an output signal having a substantially constant second frequency wherein the ratio of said first frequency to said second frequency is comprised of a whole number X and a fraction Y/z to take the form XY/z, comprising: first counter means responsive to said input signal and to a first control signal for providing successive sub-groups of cycles at a rate corresponding to said second frequency as said output signal, said cycles comprising low count sub-groups containing X cycles at said first frequency and high count sub-groups containing X+1 cycles at said first frequency, second counter means responsive to the operation of said first counter means and to a second control signal for counting the positions of successive sub-groups of cycles of said output signal, the number of said successive sub-groups of cycles being z, and control means for providing said first control signal to said first counter means to select the order of said successive sub-groups so that a maximum error in said output signal is equal to or less than the time period of said first frequency.
Claim 6
Dependent Claim
198 words
A frequency synthesizer responsive to a selected one of a plurality of input signals having a first frequency for providing an output signal having a substantially constant second frequency wherein the ratio of said first frequency to said second frequency is comprised of a whole number X and a fraction Y/z to take the form XY/z, comprising: first counter means responsive to said input signal and to a first control signal for providing successive sub-groups of cycles at a rate corresponding to said second frequency as said output signal, said cycles comprising low count sub-groups containing X cycles at said first frequency and high count sub-groups containing X+1 cycles at said first frequency, second counter means responsive to the operation of said first counter means and to a second control signal for counting the positions of successive sub-groups of cycles of said output signal, the number of said successive sub-groups of cycles being z, and control means for providing said first control signal to said first counter means to select the order of said successive sub-groups so that a maximum error in said output signal is equal to or less than the time period of said first frequency.
Claim 7
Dependent Claim
135 words
The frequency synthesizer of claim 4 wherein said input signal is selected from a plurality of input signals each having a different one of a plurality of different fixed frequencies, said frequencies being of the same order of magnitude as, or higher than, said substantially constant second frequency and said control means further comprises: memory means responsive to a control signal corresponding to a selected input signal for providing outputs representing a low count number X, a high count number X+1, a high count sub-group number y, and a total sub-group number z related to said first frequency is selected from said plurality of different fixed frequencies, and said first counter means is responsive to said low count number or said high count number and to said selected input signal to provide said output signal.
Claim 8
Independent Claim
260 words
A method for generating an output signal having a substantially constant output frequency in response to a selected one of a plurality of input signals each having a different, fixed input frequency, the frequencies of said plurality of input signals being of the same order of magnitude as, or higher than, said substantially constant output frequency, wherein the ratio of said input frequency to said output frequency is comprised of a whole number X and a fraction Y/z to take the form XY/z, said method comprising the steps of: (a) selecting an input signal from said plurality thereof having a fixed input frequency; (b) generating successive sub-groups of output cycles at a rate substantially corresponding to said output frequency wherein said successive sub-groups of cycles selectively include cycles corresponding to low count sub-groups containing X cycles at the input frequency of said selected input signal and cycles corresponding to high count sub-groups containing X+1 cycles at the frequency of said selected input signal; (c) counting the positions of said successive sub-groups of cycles to determine successive recycle periods, each said recycle period containing a recycle number z of said successive groups of cycles, and (d) responsive to step (c), selecting said successive sub-groups of output cycles to produce said output signal which includes cycles corresponding to Y high count sub-groups and to z-Y low count sub-groups in a selected order in each z successive sub-groups so that a maximum error in said output signal is equal to or less than the time period of the frequency of said input signal.
Claim 9
Independent Claim
260 words
A method for generating an output signal having a substantially constant output frequency in response to a selected one of a plurality of input signals each having a different, fixed input frequency, the frequencies of said plurality of input signals being of the same order of magnitude as, or higher than, said substantially constant output frequency, wherein the ratio of said input frequency to said output frequency is comprised of a whole number X and a fraction Y/z to take the form XY/z, said method comprising the steps of: (a) selecting an input signal from said plurality thereof having a fixed input frequency; (b) generating successive sub-groups of output cycles at a rate substantially corresponding to said output frequency wherein said successive sub-groups of cycles selectively include cycles corresponding to low count sub-groups containing X cycles at the input frequency of said selected input signal and cycles corresponding to high count sub-groups containing X+1 cycles at the frequency of said selected input signal; (c) counting the positions of said successive sub-groups of cycles to determine successive recycle periods, each said recycle period containing a recycle number z of said successive groups of cycles, and (d) responsive to step (c), selecting said successive sub-groups of output cycles to produce said output signal which includes cycles corresponding to Y high count sub-groups and to z-Y low count sub-groups in a selected order in each z successive sub-groups so that a maximum error in said output signal is equal to or less than the time period of the frequency of said input signal.
References Cited (Backward Citations)
US3230352A
Cited
US3538442A
Cited
US3909791A
Cited
US3863224A
Cited
US3840724A
Cited
US3937932A
Cited
US4031476A
Cited
US4084082A
Cited
US4184068A
Cited
US4357527A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-07 | 1988-02-06 | 1988-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-07 | 1992-02-06 | 1992-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-07 | 1996-02-06 | 1996-08-07 | $7700.00 | Window Closed / Lapsed |