Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
205 words
A bus control circuit (22,18) for controlling a computer system (10) to which a master circuit (14) and a slave circuit (16) can be connected, characterised in that the bus control circuit (22) comprises: a synchronous bus (18) including a clock path, a master speed indication path for connection to the master circuit (14), and a slave speed indication path for connection to a slave circuit (16); a clock generation circuit (26) for generating a first clock signal having a first clock frequency or a second clock signal having a second clock frequency, and a monitor control circuit (24), the clock generation circuit (26) being configured to provide the second clock signal to the clock path in response to a control signal, and otherwise to provide the first clock signal on the clock path; and a monitor clock control circuit (24) for receiving a master speed indication signal from the master speed indication path and a slave. speed indication signal from the slave speed indication path, the monitor clock control circuit (24) being configured to generate the control signal when the master and slave speed indication signals indicate that the master circuit (14) and the slave circuit (16) may both operate at the second frequency.
Claim 2
Dependent Claim
28 words
A bus control circuit (22,18) as claimed in claim 1 wherein the clock generation circuit (26) generates the first and second clock signals from a single clock (28).
Claim 3
Dependent Claim
51 words
A bus control circuit (22,18) as claimed in claim 2 wherein the clock generation circuit (26) comprises: a selection circuit (34) configured to select one of the first and second clock signals, and a divider circuit (36) configured to generate the first and second clock signals from the single clock (28).
Claim 4
Dependent Claim
25 words
A bus control circuit (22,18) as claimed in any preceding claim wherein the second clock frequency is an even multiple of the first clock frequency.
Claim 5
Dependent Claim
27 words
A bus control circuit (22,18) as claimed in any claim preceding claim 5 wherein the second clock frequency is an odd multiple of the first clock frequency.
Claim 6
Dependent Claim
35 words
A bus control circuit (22,18) as claimed in any preceding claim wherein the monitor clock control circuit is configured to generate the control signal in response to active low master and slave speed indication signals.
Claim 7
Dependent Claim
22 words
A computer system (10) comprising a central processing unit (20) and a bus control circuit (22,18) as claimed in any preceding claim
Claim 8
Dependent Claim
61 words
A computer system (10) as claimed in claim 7 comprising a master circuit (14) and a slave circuit (16) connected to the bus (18), the master circuit (14) having a master speed indication circuit (15) for generating the master speed indication signal, and the slave circuit (16) having a slave speed indication circuit (17) for generating the slave speed indication signal.
Claim 9
Dependent Claim
19 words
A computer system as claimed in claim 8 wherein the master circuit (14) includes the bus control circuit (22).
Claim 10
Independent Claim
158 words
A method for transferring information between first and second elements (14, 16) of a computer system (10) in which elements (14, 16) communicate via a multibit bus (18), the communication being synchronous with a first clock signal having a first frequuency, the bus (18) including a clock path through which the clock signal is provided to the elements, the method comprising generating a first speed indication signal indicating the operating speed of said first element (14), generating a second speed indication signal indicating the operating speed of said second element (16), and providing a second clock signal having a second frequency to said first and second elements via (14, 16) said clock path when said first speed indication signal and said second speed indication signal indicate that said first and second elements (14, 16) may both communicate at said second frequency, said first and second clock signals being provided to said clock path on a mutually exclusive basis.