US5912928A
Expired / Lapsed
US
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High speed serial data transmission encoder
Assignee: MediaTek Inc
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Filing: 1997-06-27
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Granted: 1999-06-15
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Expires: 2017-06-27
Abstract
Abstract A clock encoding circuit, e.g., for Manchester encoding, for high speed data transmission (IEEE 1394) and a circuit for controlling data and encoded clock transmission. The clock encoding circuit includes two parallel to serial shift registers, a DATA register and a STROBE register, receiving data in parallel and shifted out at 100 MHz, 200 MHz or 400 MHz. The STROBE register receives every other bit of the data inverted. When both registers are clocked at the data transmission rate, data is shifted out of DATA register and the transmission clock is encoded in STROBE, shifted out of the STROBE register. Bit inversion may be with invertors receiving data as it is passed to the DATA register, or alternatively, after it is loaded into the DATA register. The circuit for controlling DATA and STROBE transmission includes the clock encoding circuit, a frequency matching register array and a loopback shift register. A control word is loaded into the loopback register and loops through the loopback register at the transmission rate, triggering data transfers from the frequency matching register array to the DATA and STROBE registers. All or part of the DATA and STROBE register contents is transmitted depending on the transmission rate.
Inventors
- 👤 Leonard R. Chieco
- 👤 Louis T. Fasano
- 👤 Keith W. Heilmann
- 👤 Michael A. Sorna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:37
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0008; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
144 words
A clock encoding circuit, for high speed data transmission such as for Manchester encoding, said clock encoding circuit comprising: a first register, said first register being a parallel to serial shift register receiving data in parallel and being clocked at a data transmission rate, said data being shifted and transmitted at said data transmission rate as a serial data signal; and a second register, said second register being a parallel to serial shift register clocked at said data transmission rate, said second register receiving altered data in parallel, every other bit of said altered data being inverted from data received by said first register, said altered data being clocked and shifted and transmitted at said data transmission rate as a strobe signal, whereby signal delay between said data received by said first register and said altered data received by said second register is minimized.
Claim 2
Dependent Claim
144 words
A clock encoding circuit, for high speed data transmission such as for Manchester encoding, said clock encoding circuit comprising: a first register, said first register being a parallel to serial shift register receiving data in parallel and being clocked at a data transmission rate, said data being shifted and transmitted at said data transmission rate as a serial data signal; and a second register, said second register being a parallel to serial shift register clocked at said data transmission rate, said second register receiving altered data in parallel, every other bit of said altered data being inverted from data received by said first register, said altered data being clocked and shifted and transmitted at said data transmission rate as a strobe signal, whereby signal delay between said data received by said first register and said altered data received by said second register is minimized.
Claim 3
Dependent Claim
33 words
The clock encoding circuit of claim 1 further comprising a plurality of invertors, each said every other data bit being inverted by one of said plurality of invertors to provide said altered data.
Claim 4
Dependent Claim
28 words
The clock encoding circuit of claim 2 wherein the plurality of invertors are connected between parallel inputs of said first register and parallel inputs of said second register.
Claim 5
Dependent Claim
28 words
The clock encoding circuit of claim 2 wherein the plurality of invertors are connected between parallel outputs of said first register and parallel inputs of said second register.
Claim 6
Dependent Claim
61 words
An Integrated Circuit (IC) chip including a data transmission circuit, said data transmission circuit including the clock encoding circuit of claim 1 and further comprising: a frequency matching register array storing data to be passed to said clock encoding circuit for transmission; and, a loopback shift register controlling data transfers between said frequency matching register array and said clock encoding circuit.
Claim 7
Dependent Claim
88 words
An Integrated Circuit (IC) chip including a data transmission circuit comprising: a clock encoding circuit encoding a transmission clock into data to generate a STROBE signal; a frequency matching register array storing data to be passed to said clock encoding circuit for transmission; and, a loopback shift register controlling data transfers between said frequency matching register array and said clock encoding circuit, wherein the number transmitted of bits from each frequency matching register array location is determined by a control word shifted through said loop back shift register.
Claim 8
Dependent Claim
88 words
An Integrated Circuit (IC) chip including a data transmission circuit comprising: a clock encoding circuit encoding a transmission clock into data to generate a STROBE signal; a frequency matching register array storing data to be passed to said clock encoding circuit for transmission; and, a loopback shift register controlling data transfers between said frequency matching register array and said clock encoding circuit, wherein the number transmitted of bits from each frequency matching register array location is determined by a control word shifted through said loop back shift register.
Claim 9
Dependent Claim
117 words
The Integrated Circuit (IC) chip of claim 6 wherein the clock encoding circuit comprises: a first register, said first register being a parallel to serial shift register receiving data in parallel and being clocked at a data transmission rate, said data being shifted and transmitted at said data transmission rate as a serial data signal; and a second register, said second register being a parallel to serial shift register clocked at said data transmission rate, said second register receiving altered data in parallel, every other bit of said altered data being inverted from data received by said first register, said altered data being clocked and shifted and transmitted at said data transmission rate as a strobe signal.
Claim 10
Dependent Claim
39 words
The Integrated Circuit (IC) chip of claim 7 wherein the clock encoding circuit further comprises a plurality of invertors, each said every other data bit being inverted by one of said plurality of invertors to provide said altered data.
Claim 11
Dependent Claim
29 words
The Integrated Circuit (IC) chip of claim 8 wherein the plurality of invertors are connected between parallel inputs of said first register and parallel inputs of said second register.
Claim 12
Dependent Claim
29 words
The Integrated Circuit (IC) chip of claim 8 wherein the plurality of invertors are connected between parallel outputs of said first register and parallel inputs of said second register.
Claim 13
Dependent Claim
197 words
An Integrated Circuit (IC) chip including a Manchester encoding data transmission circuit comprising: a frequency matching register array storing data to be transmitted; a first parallel to serial shift register receiving data in parallel from said frequency matching register array and being clocked at a data transmission rate, said received data being shifted and transmitted at said data transmission rate as a serial data signal; a second parallel to serial shift register clocked at said data transmission rate; a plurality of invertors, every other bit of said received data being inverted by one of said plurality of invertors, said second parallel to serial shift register receiving altered data in parallel, said altered data being inverted data bits from said invertors and uninverted bits received by said first parallel to serial shift register, said altered data being shifted and transmitted at said data transmission rate as a strobe signal; and, a loopback shift register controlling data transfers between said frequency matching register array and said first and second parallel to serial registers, wherein the number of bits transmitted from each frequency matching register array location is determined by a control word being shifted through said loopback shift register.
Claim 14
Dependent Claim
197 words
An Integrated Circuit (IC) chip including a Manchester encoding data transmission circuit comprising: a frequency matching register array storing data to be transmitted; a first parallel to serial shift register receiving data in parallel from said frequency matching register array and being clocked at a data transmission rate, said received data being shifted and transmitted at said data transmission rate as a serial data signal; a second parallel to serial shift register clocked at said data transmission rate; a plurality of invertors, every other bit of said received data being inverted by one of said plurality of invertors, said second parallel to serial shift register receiving altered data in parallel, said altered data being inverted data bits from said invertors and uninverted bits received by said first parallel to serial shift register, said altered data being shifted and transmitted at said data transmission rate as a strobe signal; and, a loopback shift register controlling data transfers between said frequency matching register array and said first and second parallel to serial registers, wherein the number of bits transmitted from each frequency matching register array location is determined by a control word being shifted through said loopback shift register.
Claim 15
Dependent Claim
37 words
The Integrated Circuit (IC) chip of claim 11 wherein the plurality of invertors are connected between parallel inputs of said first parallel to serial shift register and parallel inputs of said second parallel to serial shift register.
Claim 16
Dependent Claim
37 words
The Integrated Circuit (IC) chip of claim 11 wherein the plurality of invertors are connected between parallel outputs of said first parallel to serial shift register and parallel inputs of said second parallel to serial shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-14 | 2002-12-14 | 2003-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-14 | 2006-12-14 | 2007-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-14 | 2010-12-14 | 2011-06-15 | $7700.00 | Window Closed / Lapsed |