Method and circuitry for extracting clock signal from received biphase modulated signal

Claim 3

A circuit arrangement for extracting a clock signal from a received biphase modulated signal, which comprises: a first detector having an input thereof coupled to receive the biphase modulated signal, said first detector being arranged to detect time points at each of which a code ONE of the received biphase modulated signal changes to a code ZERO; a second detector having an input thereof coupled to receive the biphase modulated signal, said second detector being arranged to detect time points at each of which a code ZERO of the received biphase modulated signal changes to a code ONE; a set-and-reset type flip-flop having one input coupled to one of said first and second detectors, and having another input coupled to the other one of said first and second detectors; and an exclusive OR circuit which receives an output of the flip-flop and the transmitted biphase modulated signal, whereby said clock signal is obtainable at an output of said exclusive OR circuit.

Claim 4

A circuit arrangement for extracting a clock signal from a received biphase modulated signal, which comprises: a first detector having an input thereof coupled to receive the biphase modulated signal, said first detector being arranged to detect time points at each of which a code ONE of the received biphase modulated signal changes to a code ZERO; a second detector having an input thereof coupled to receive the biphase modulated signal, said second detector being arranged to detect time points at each of which a code ZERO of the received biphase modulated signal changes to a code ONE; a set-and-reset type flip-flop having one input coupled to one of said first and second detectors, and having another input coupled to the other one of said first and second detectors; and an exclusive OR circuit which receives an output of the flip-flop and the transmitted biphase modulated signal, whereby said clock signal is obtainable at an output of said exclusive OR circuit.

Claim 5

A circuit arrangement as claimed in claim 2, wherein said first detector includes an inverter having an output thereof coupled to receive the biphase modulated signal, a delay circuit and an AND circuit, said AND circuit having one input coupled to an output of said inverter and having another input coupled via said delay circuit to an output of said inverter; and wherein said second detector includes another delay circuit and another AND circuit, said other AND circuit having one input coupled to receive the biphase modulated signal and having another input coupled to receive via said other delay circuit the received biphase modulated signal.

Claim 6

A circuit arrangement for extracting a clock signal from a received biphase modulated signal, which comprises: a detector having an input thereof coupled to receive the biphase modulated signal, said detector being arranged to detect time points at each of which a code ONE of the received biphase modulated signal changes to a code ZERO or vice versa; a binary counter having an input thereof coupled to receive an output of said detector; and an exclusive OR circuit having one input coupled to receive an output of said binary counter and another input coupled to receive the biphase modulated signal, whereby the clock signal is obtainable at the output of said exclusive OR circuit.

Claim 7

A circuit arrangement for extracting a clock signal from a received biphase modulated signal, which comprises: a detector having an input thereof coupled to receive the biphase modulated signal, said detector being arranged to detect time points at each of which a code ONE of the received biphase modulated signal changes to a code ZERO or vice versa; a binary counter having an input thereof coupled to receive an output of said detector; and an exclusive OR circuit having one input coupled to receive an output of said binary counter and another input coupled to receive the biphase modulated signal, whereby the clock signal is obtainable at the output of said exclusive OR circuit.

Claim 8

A circuit arrangement for extracting a clock signal from a received biphase modulated signal, which comprises: a detector having an input thereof coupled to recieve the biphase modulated signal, said detector being arranged to detect time points at each of which a code ONE of the received biphase modulated signal changes to a code ZERO or vice versa, said detector including an inverter having an input thereof coupled to receive the biphase modulated signal, first and second delay circuits, a first AND circuit having one input coupled to receive the output of said inverter and another input coupled via said first delay circuit to receive an output of said inverter, a second AND circuit having one input coupled to receive the biphase modulated signal and another input coupled via said second delay circut to receive the biphase modulated signal, and an OR circuit having two inputs coupled to the outputs of said first and second AND gates; a binary counter having an input thereof coupled to receive an output of said detector; an exclusive OR circuit having one input coupled to receive an output of said binary counter and another input coupled to receive the biphase modulated signal, whereby the clock signal is obtainable at the output of said exclusive OR circuit.

Claim 9

A circuit arrangement for extracting a clock signal from a received biphase modulated signal, which comprises: a detector having an input thereof coupled to recieve the biphase modulated signal, said detector being arranged to detect time points at each of which a code ONE of the received biphase modulated signal changes to a code ZERO or vice versa, said detector including an inverter having an input thereof coupled to receive the biphase modulated signal, first and second delay circuits, a first AND circuit having one input coupled to receive the output of said inverter and another input coupled via said first delay circuit to receive an output of said inverter, a second AND circuit having one input coupled to receive the biphase modulated signal and another input coupled via said second delay circut to receive the biphase modulated signal, and an OR circuit having two inputs coupled to the outputs of said first and second AND gates; a binary counter having an input thereof coupled to receive an output of said detector; an exclusive OR circuit having one input coupled to receive an output of said binary counter and another input coupled to receive the biphase modulated signal, whereby the clock signal is obtainable at the output of said exclusive OR circuit.