Split phase code synchronizer and demodulator

Claim 2

A synchronizer for receiving encoded data of the split phase clock synchronous encoded type and recovering the clock signal therefrom, comprising: reference signal means selectable to produce either a first or a second reference signal, each reference signal having the same frequency as the clock signal at a phase angle of 180° with respect to the other signal; synchronous detecting means for synchronously detecting the received encoded data with the selected reference signal; integrator means for producing an integral signal having a value representative of the integral of the synchronous detecting means output over each cycle of the selected reference signal; comparator means for producing an error signal in response to the integral signal having a value within predetermined minimum and maximum values; and control logic means for processing the error signals and selecting the alternate output from the reference signal means responsive to a predetermined condition thereof, whereby the selected reference signal is synchronized to the clock signal.

Claim 3

The synchronizer of claim 1 wherein the reference signal means comprises: differentiating means for producing a pulse at each transition of the receiver encoded data; bandpass filter means for processing the transition pulses from the differentiating means and passing the signal components thereof which are at twice the clock frequency; a phase locked loop for producing an oscillator output signal which is in phase quadrature with the bandpass filter passed signal; and a bistable circuit operative to divide the oscillator output signal by two, the bistable including means adapted to respond to a received trigger signal to produce its divided output either at 0° or 180° relative phase.

Claim 4

The synchronizer of claim 1 wherein the synchronous detecting means is comprised of an exclusive OR gate.

Claim 5

The synchronizer of claim 1 wherein the control logic means comprises: means to generate correct signals in response to the integral signal exceeding said predetermined upper or lower limits; and counter means for processing both the comparator produced error signals and said generated correct signals and activating the reference signal means to select the alternate reference signal in response to a predetermined relationship therebetween.

Claim 6

A synchronizer for receiving encoded data of the split phase, clock derived type and regenerating the properly phased clock signal thereof, comprising: oscillator means for generating an oscillator signal which is in predetermined phase relationship with the clock signal and is at twice the frequency thereof; divider means for producing first and second signals, each signal having a frequency of one-half the oscillator frequency, the two signals having a relative phase angle of 180° with respect to each other; selecting means for selecting either the first or the second signal; logic gate means for processing the received data with the selected first or second signal and producing a first logic level output in response to said processed signals synchronously assuming the same logic state, the logic gate otherwise producing a second logic level; integrator means for integrating the logic gate means produced signal over each cycle of the selected first or second signal and producing an analog signal representative of said integral; comparator means for producing an error signal in response to the integrator produced analog signal being within predetermined upper and lower limits; and control logic means for processing the comparator produced error signals and activating the selecting means to select the alternate signal in response to a predetermined error signal condition, whereby the produced output of the divider means tends to be the regenerated and properly phased clock signal.

Claim 7

A synchronizer for receiving encoded data of the split phase, clock derived type and regenerating the properly phased clock signal thereof, comprising: oscillator means for generating an oscillator signal which is in predetermined phase relationship with the clock signal and is at twice the frequency thereof; divider means for producing first and second signals, each signal having a frequency of one-half the oscillator frequency, the two signals having a relative phase angle of 180° with respect to each other; selecting means for selecting either the first or the second signal; logic gate means for processing the received data with the selected first or second signal and producing a first logic level output in response to said processed signals synchronously assuming the same logic state, the logic gate otherwise producing a second logic level; integrator means for integrating the logic gate means produced signal over each cycle of the selected first or second signal and producing an analog signal representative of said integral; comparator means for producing an error signal in response to the integrator produced analog signal being within predetermined upper and lower limits; and control logic means for processing the comparator produced error signals and activating the selecting means to select the alternate signal in response to a predetermined error signal condition, whereby the produced output of the divider means tends to be the regenerated and properly phased clock signal.

Claim 8

The synchronizer of claim 5 wherein the oscillator means comprises a phase locked loop.

Claim 9

The synchronizer of claim 5 wherein the oscillator means comprises: differentiating means for producing a pulse at each transition of the received encoded data; bandpass filter means for processing the transition pulses from the differentiating means and passing those signal components thereof which are twice the clock frequency; and a phase locked loop for producing an oscillator output signal which is in phase quadrature with the bandpass filter passed signal.

Claim 10

The synchronizer of claim 5 wherein the logic state means is comprised of an exclusive OR gate.

Claim 11

The synchronizer of claim 5 wherein the control logic means comprises: means to generate correct signals in response to the integrator produced analog signal exceeding said predetermined upper or lower limits; and counter means for processing both the comparator produced error signals and said generated correct signals and activating the selecting means to select the alternate first or second signal in response to a predetermined relationship therebetween.

Claim 12

The synchronizer of claim 5 in combination with demodulator means for decoding said received data, said combination comprising: sample pulse generating means for producing a sample pulse at a predetermined point in each cycle of the selected first or second signal; and data sample means for producing a recovered data signal having predetermined first or second levels responsive to the status of the integrator produced logic level at the time of each produced sample pulse.

Claim 13

A demodulator for receiving and decoding data of the split phase, clock synchronous encoded type, comprising: reference signal means selectable to produce either a first or a second reference signal, each reference signal having the same frequency as the clock frequency at a phase angle of 180° with respect to the other signal; synchronous detecting means for synchronously detecting the received encoded data with the selected reference signal; integrator means for producing an integral signal having a value representative of the integral of the synchronous detecting means output over each cycle of the selected reference signal; comparator means for producing an error signal in response to the integral signal having a value within predetermined minimum and maximum values; control logic means for processing the error signals and selecting the alternate output from the reference signal means responsive to a predetermined condition thereof; sample pulse generating means for producing a sample pulse at a predetermined point in each cycle of the selected reference signal; and decoded data output means for producing an output signal having either a first or a second logic level responsive to the status of the integral signal synchronous to the occurrence of each sample pulse.

Claim 14

A demodulator for receiving and decoding data of the split phase, clock synchronous encoded type, comprising: reference signal means selectable to produce either a first or a second reference signal, each reference signal having the same frequency as the clock frequency at a phase angle of 180° with respect to the other signal; synchronous detecting means for synchronously detecting the received encoded data with the selected reference signal; integrator means for producing an integral signal having a value representative of the integral of the synchronous detecting means output over each cycle of the selected reference signal; comparator means for producing an error signal in response to the integral signal having a value within predetermined minimum and maximum values; control logic means for processing the error signals and selecting the alternate output from the reference signal means responsive to a predetermined condition thereof; sample pulse generating means for producing a sample pulse at a predetermined point in each cycle of the selected reference signal; and decoded data output means for producing an output signal having either a first or a second logic level responsive to the status of the integral signal synchronous to the occurrence of each sample pulse.

Claim 15

The demodulator of claim 11 wherein the reference signal means comprises: differentiating means for producing a pulse at each transition of the received encoded data; bandpass filter means for processing the transition pulses from the differentiating means and passing the signal components thereof which are at twice the clock frequency; a phase locked loop for producing an oscillator output signal which is in phase quadrature with the bandpass filter passed signal; and a bistable circuit operative to divide the oscillator output signal by two, the bistable including means adapted to respond to a received trigger signal to produce its divided output either at 0° or 180° relative phase.

Claim 16

The demodulator of claim 11 wherein the synchronous detecting means is comprised of an exclusive OR gate.

Claim 17

The demodulator of claim 11 wherein the control logic means comprises: means to generate correct signal in response to the integral signal exceeding said predetermined upper or lower limits; and counter means for processing both the comparator produced error signals and said generated correct signals and activating the reference signal means to select the alternate reference signal in response to a predetermined relationship therebetween.

Claim 18

The demodulator of claim 11 wherein the decoded output data means comprises a D type flip flop with the integral signal coupled to its D input and the sample pulses coupled to its clock input whereby its Q output produces the decoded data.