US3967062A
Expired / Lapsed
US
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Method and apparatus for encoding data and clock information in a self-clocking data stream
Assignee: NCR Voyix Corp
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Filing: 1975-03-05
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Granted: 1976-06-29
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Expires: 1995-03-05
Abstract
Abstract A method and apparatus is described for generating a data stream incorporating a self-clocking Manchester type code. The data, originally stored in a shift register, is shifted out of the register in bi-level form with a first voltage level representing one binary value and a second voltage level representing a second binary value. The output voltage levels from the shift register are applied simultaneously to two AND gates with an inverter interposed between the shift register and one of the AND gates. Two clock pulse trains are utilized, one having a clock rate twice the clock rate of the other. The clock pulses are respectively applied to the AND gates, the outputs of which are OR'ed and applied to a flip-flop. The output pulses from the OR-gate clocks the flip-flop which toggles to provide a suitably encoded self-clocking data stream at the true and the not true outputs thereof. The output from the flip-flop is applied to a line driver for driving a transmission cable that may be of the twin co-axial type.
Inventors
- 👤 Joseph J. Dobias
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:44
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
170 words
A method of encoding and transmitting binary information, represented by a wave form having a first voltage level during a bit period indicating one binary value and a second voltage level during a bit period indicating a second binary value, into a bi-phase self-clocking bit stream, comprising the steps of: a. providing a first clock pulse train having a first pulse rate; b. providing a second clock pulse train having a second pulse rate; c. applying to a common terminal either said first clock pulse train when said wave form is at said first level during a bit period or said second clock pulse train when said wave form is at said second level during a bit period; and d. providing an output wave form having two voltage levels and including two voltage level transitions during said bit period when said second clock pulse train occurs at said terminal and having a single voltage level transition during said bit period when said first clock pulse train occurs at said terminal.
Claim 2
Independent Claim
170 words
A method of encoding and transmitting binary information, represented by a wave form having a first voltage level during a bit period indicating one binary value and a second voltage level during a bit period indicating a second binary value, into a bi-phase self-clocking bit stream, comprising the steps of: a. providing a first clock pulse train having a first pulse rate; b. providing a second clock pulse train having a second pulse rate; c. applying to a common terminal either said first clock pulse train when said wave form is at said first level during a bit period or said second clock pulse train when said wave form is at said second level during a bit period; and d. providing an output wave form having two voltage levels and including two voltage level transitions during said bit period when said second clock pulse train occurs at said terminal and having a single voltage level transition during said bit period when said first clock pulse train occurs at said terminal.
Claim 3
Dependent Claim
29 words
The method of claim 1, including the step of providing a second clock pulse train at a bit rate twice the bit rate of said first clock pulse train.
Claim 4
Dependent Claim
34 words
The method of claim 1, wherein the step of providing an output wave form includes providing voltage level transitions in said wave form occurring at only the beginning and mid-point of each bit period.
Claim 5
Dependent Claim
250 words
Apparatus for encoding and transmitting binary information, represented by a wave form having a first voltage level during a bit period indicating one binary value and a second voltage level during a bit period indicating a second binary value, into a bi-phase self-clocking bit stream, comprising: a. storage means for temporarily storing binary information for transmitting said information in the form of said wave form; b. a first gate connected to said storage means for receiving said wave form, said gate being enabled by said first voltage level; c. means connected to said storage means for receiving said wave form and for changing said first level to said second level and changing said second level to said first level; d. a second gate connected to said means connected to said storage means, said second gate being enabled by said second voltage level when said second voltage level has been changed to said first voltage level; e. means for applying a first clock pulse train to said first gate; f. means for applying a second clock pulse train to said second gate; g. said first clock pulse train having a pulse rate twice that of said second clock pulse train; and h. a flip-flop connected to said first and second gates for receiving clock pulses therefrom, said flip-flop having first and second output voltage levels, said flip-flop changing state to provide an output voltage level transition from one level to another in response to each clock pulse received from said gates.
Claim 6
Dependent Claim
250 words
Apparatus for encoding and transmitting binary information, represented by a wave form having a first voltage level during a bit period indicating one binary value and a second voltage level during a bit period indicating a second binary value, into a bi-phase self-clocking bit stream, comprising: a. storage means for temporarily storing binary information for transmitting said information in the form of said wave form; b. a first gate connected to said storage means for receiving said wave form, said gate being enabled by said first voltage level; c. means connected to said storage means for receiving said wave form and for changing said first level to said second level and changing said second level to said first level; d. a second gate connected to said means connected to said storage means, said second gate being enabled by said second voltage level when said second voltage level has been changed to said first voltage level; e. means for applying a first clock pulse train to said first gate; f. means for applying a second clock pulse train to said second gate; g. said first clock pulse train having a pulse rate twice that of said second clock pulse train; and h. a flip-flop connected to said first and second gates for receiving clock pulses therefrom, said flip-flop having first and second output voltage levels, said flip-flop changing state to provide an output voltage level transition from one level to another in response to each clock pulse received from said gates.
Claim 7
Dependent Claim
22 words
The apparatus claimed in claim 4, including a line driver connected to receive said output wave form for driving a transmission cable.
Claim 8
Dependent Claim
251 words
Apparatus for encoding and transmitting binary information, represented by a wave form having a first voltage level during a bit period indicating one binary value and a second voltage level during a bit period indicating a secondary binary value, into a bi-phase self-clocking bit stream, comprising: a. a shift register for temporarily storing binary information and for transmitting said information in the form of said wave form; b. a first AND gate connected to said shift register for receiving said wave form, said AND gate being enabled by said first voltage level; c. an inverter connected to said shift register for receiving and inverting said wave form; d. a second AND gate connected to said inverter for receiving said inverted wave form, said second AND gate being enabled by said second voltage level when said wave form is inverted; e. means for applying a first clock pulse train to said first AND gate; f. means for applying a second clock pulse train to said second AND gate; g. said first clock pulse train having a pulse rate twice that of said second clock pulse train; h. an OR-gate connected to said first and second AND gates; and i. a flip-flop connected to said OR-gate for receiving clock pulses from said first and second AND gates, said flip-flop having first and second output voltage levels, said flip-flop changing state to provide an output voltage level transition from one level to another in response to each clock pulse received from said AND gates.
Claim 9
Dependent Claim
251 words
Apparatus for encoding and transmitting binary information, represented by a wave form having a first voltage level during a bit period indicating one binary value and a second voltage level during a bit period indicating a secondary binary value, into a bi-phase self-clocking bit stream, comprising: a. a shift register for temporarily storing binary information and for transmitting said information in the form of said wave form; b. a first AND gate connected to said shift register for receiving said wave form, said AND gate being enabled by said first voltage level; c. an inverter connected to said shift register for receiving and inverting said wave form; d. a second AND gate connected to said inverter for receiving said inverted wave form, said second AND gate being enabled by said second voltage level when said wave form is inverted; e. means for applying a first clock pulse train to said first AND gate; f. means for applying a second clock pulse train to said second AND gate; g. said first clock pulse train having a pulse rate twice that of said second clock pulse train; h. an OR-gate connected to said first and second AND gates; and i. a flip-flop connected to said OR-gate for receiving clock pulses from said first and second AND gates, said flip-flop having first and second output voltage levels, said flip-flop changing state to provide an output voltage level transition from one level to another in response to each clock pulse received from said AND gates.
Claim 10
Dependent Claim
21 words
The apparatus of claim 6, including a line driver connected to receive said output wave form for driving a transmission cable.
References Cited (Backward Citations)
US3629505A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-29 | 1979-12-29 | 1980-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-29 | 1983-12-29 | 1984-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-29 | 1987-12-29 | 1988-06-29 | $7700.00 | Window Closed / Lapsed |