Coded data enhancer,synchronizer,and parity remover systems

Claim 2

In a method of enhancing binary transitions with the aid of a register in a first stream of binary words accompanied by a first series of clock pulses, each word having n bits and being accompanied by n clock pulses, the improvement comprising in combination the steps of: providing a second series of clock pulses having (n+1) clock pulses for each n clock pulses of the first series; providing a second stream of binary words in which each binary word of said first stream is accommodated within n clock pulses of said (n+1) clock pulses of said second series; and providing binary words in said second stream with parity bits during clock pulses outside the n clock pulses within which each binary word is accommodated in said second stream; said second stream of binary words including said parity bits being provided by transferring each binary word of said first stream into said register, determining the parity of each binary word during transfer of that binary word into said register, providing each binary word in said register with a parity bit corresponding to the determined parity of that binary word, and shifting each binary word with parity bit out of said register with said second series of clock pulses.

Claim 3

A method as claimed in claim 1, including the steps of: determining during the transfer of each word into said register whether the particular word has an even number or an odd number of binary bits of a predetermined kind; and providing each word in said register with a first kind of parity bit when the particular word has an even number of binary bits of said predetermined kind, and with a second kind of parity bit when the particular word has an odd number of binary bits of said predetermined kind.

Claim 4

A method as claimed in claim 1, including the steps of: determining during the transfer of each word into said register whether the particular word has an even number or an odd number of binary ones; and providing each word in said register with a binary one as a parity bit when the particular word has an even number of binary ones, and with a binary zeRo as a parity bit when the particular word has an odd number of binary ones.

Claim 5

A method as claimed in claim 1, including the steps of: providing a first shift register for processing n bits; providing a second shift register for processing (n+1) bits; clocking said first shift register with said first series of clock pulses; shifting each word in said first stream into said first shift register; transferring the bits of each word from said first shift register to said second shift register; determining during the transfer of the bits of each word from the first register to the second register whether the particular word has an even number or an odd number of binary bits of a predetermined kind; providing each word in said second shift register with a first kind of parity bit when the particular word has an even number of binary bits of said predetermined kind, and with a second kind of parity bit when the particular word has an odd number of binary bits of said predetermined kind; and shifting each word with parity bit out of said second shift register with said second series of clock pulses.

Claim 6

A method as claimed in claim 1, including the steps of: providing a first shift register for processing n bits; providing a second shift register for processing (n+1) bits; clocking said first shift register with said first series of clock pulses; shifting each word in said first stream into said first shift register; transferring the bits of each word from said first shift register to said second shift register; determining during the transfer of the bits of each word from the first register to the second register whether the particular word has an even number or an odd number of binary ones; providing each word in said second shift register with a binary one as a parity bit when the particular word has an even number of binary ones, and with a binary zero as a parity bit when the particular word has an odd number of binary ones; and shifting each word with parity bit out of said second shift register with said second series of clock pulses.

Claim 7

A method as claimed in claim 5, including the steps of: providing a parity generator having an even output circuit for generating a binary one as a parity bit in response to a determination that a binary word has an even number of binary ones; determining with said parity generator during transfer of words from the first to the second shift register whether words have an even number or an odd number of binary ones; and providing by means of said parity generator and in said second shift register each word having an even number of binary ones with a binary one as a parity bit.

Claim 8

A method as claimed in claim 5, wherein: said first shift register is operated as a serial-in-parallel-out shift register; and said second shift register is operated as a parallel-in-serial-out shift register.

Claim 9

A method as claimed in claim 1, wherein: said second series of clock pulses is provided by generating with the aid of said first series of clock pulses a signal having a frequency equal to b(n+1) times the clock pulse rate in said first series, and by generating with the aid of said signal a series of clock pulses having a rate equal to 1/bn times said frequency, wherein b is a positive number.

Claim 10

A method as claimed in claim 1, including the steps of: generating with the aid of said first series of clock pulses a first signal having a frequency equal to b(n+1) times the clock pulse rate in said first series; generating with the aid of said first signal a second signal having a pulse rate equal to 1/(b(n+1)) times the frequency of said first signal; employing said second signal in the generation of said first signal; generating with the aid of said first signal a third signal having a pUlse rate equal to 1/bn times the frequency of said first signal; and employing said third signal as said second series of clock pulses, with b being a positive number.

Claim 11

A method as claimed in claim 9, including the steps of: providing a first shift register for processing n bits; providing a second shift register for processing (n+1) bits; clocking said first shift register with said first series of clock pulses; shifting each word in said first stream into said first shift register; transferring the bits of each word from said first shift register to said second shift register; determining during the transfer of the bits of each word from the first register to the second register whether the particular word has an even number or an odd number of binary bits of a predetermined kind; providing each word in said second shift register with a first kind of parity bit when the particular word has an even number of binary bits of said predetermined kind, and with a second kind of parity bit when the particular word has an odd number of binary bits of said predetermined kind; and shifting each word with parity bit out of said second shift register with said third signal.

Claim 12

In apparatus for enhancing binary transitions in a first stream of binary words accompanied by a first series of clock pulses, each word having n bits and being accompanied by n clock pulses, the improvement comprising in combination: means for generating a second series of clock pulses having (n+1) clock pulses for each n clock pulses of the first series; means for generating a second stream of binary words in which each binary word of said first stream is accommodated within n clock pulses of said (n+1) clock pulses of said second series; and means for providing binary words in said second stream with parity bits during clock pulses outside the n clock pulses within which each binary word is accommodated in said second stream; said means for generating a second stream of binary words including register means, means connected to said register means for transferring binary words of said first stream into said register means, and means connected to said means for generating a second series of clock pulses and to said register means for shifting each binary word with parity bit out of said register means with said second series of clock pulses; and said means for providing binary words in said second stream with parity bits including means for determining the parity of each binary word during said transfer of that binary word into said register means, and means connected to said register means and to said parity determining means for providing each binary word in said register means with a parity bit corresponding to the determined parity of that binary word.

Claim 13

In apparatus for enhancing binary transitions in a first stream of binary words accompanied by a first series of clock pulses, each word having n bits and being accompanied by n clock pulses, the improvement comprising in combination: means for generating a second series of clock pulses having (n+1) clock pulses for each n clock pulses of the first series; means for generating a second stream of binary words in which each binary word of said first stream is accommodated within n clock pulses of said (n+1) clock pulses of said second series; and means for providing binary words in said second stream with parity bits during clock pulses outside the n clock pulses within which each binary word is accommodated in said second stream; said means for generating a second stream of binary words including register means, means connected to said register means for transferring binary words of said first stream into said register means, and means connected to said means for generating a second series of clock pulses and to said register means for shifting each binary word with parity bit out of said register means with said second series of clock pulses; and said means for providing binary words in said second stream with parity bits including means for determining the parity of each binary word during said transfer of that binary word into said register means, and means connected to said register means and to said parity determining means for providing each binary word in said register means with a parity bit corresponding to the determined parity of that binary word.

Claim 14

An apparatus as claimed in claim 11, wherein said means for providing binary words with parity bits include: means for determining during the transfer of each word into said register means whether the particular word has an even number or an odd number of binary bits of a predetermined kind; and means for providing each word in said register means with a first kind of parity bit when the particular word has an even number of binary bits of said predetermined kind, and with a second kind of parity bit when the particular word has an odd number of binary bits of said predetermined kind.

Claim 15

An apparatus as claimed in claim 11, wherein said means for providing binary words with parity bits include: means for determining during the transfer of each word into said register means whether the particular word has an even number or an odd number of binary ones; and means for providing each word in said register means with a binary one as a parity bit when the particular word has an even number of binary ones, and with a binary zero as a parity bit when the particular word has an odd number of binary onEs.

Claim 16

An apparatus as claimed in claim 11, wherein: said means for generating a second stream of binary words include a first shift register for processing n bits, means for clocking the first shift register with said first series of clock pulses, means for shifting each word in said first stream into said first shift register; said register means include a second shift register for processing (n+1) bits; said transferring means include means for transferring the bits in each word from the first shift register to the second shift register; said parity determining means include means for determining during the transfer of the bits of each shifted word whether the particular word has an even number or an odd number of binary bits of a predetermined kind; and said parity bits providing means connected to said register means include means for providing each word in said second shift register with a first kind of parity bit when the particular word has an even number of binary bits of said predetermined kind, and with a second kind of parity bit when the particular word has an odd number of binary bits of said predetermined kind.

Claim 17

An apparatus as claimed in claim 11, wherein: said means for generating a second stream of binary words include a first shift register for processing n bits, means for clocking the first shift register with said first series of clock pulses, means for shifting each word in said first stream into said first shift register; said register means include a second shift register for processing (n+l) bits; said transferring means include means for transferring the bits in each word from the first shift register to the second shift register; said parity determining means include means for determining during the transfer of the bits of each shifted word whether the particular word has an even number or an odd number of binary ones; and said parity bits providing means connected to said register means include means for providing each word in said second shift register with a binary one as a parity bit when the particular word has an even number of binary ones, and with a binary zero as a parity bit when the particular word has an odd number of binary ones.

Claim 18

An apparatus as claimed in claim 11, wherein: said means for generating a second stream of binary words include a first shift register for processing n bits, means for clocking the first shift register with said first series of clock pulses, means for shifting each word in said first stream into said first shift register; said register means include a second shift register for processing (n+1) bits; said transferring means include means for transferring the bits in each word from the first shift register to the second shift register; said parity determining means include parity generator means connected to said first and second shift registers and including means for determining whether words have an even number or an odd number of binary ones; and said parity bits providing means connected to said register means include means for applying to said second register a binary one as a parity bit in response to a determination that a binary word has an even number of binary ones.

Claim 19

An apparatus as claimed in claim 11, wherein said means for generating said second series of clock pulses include: first means for generating with the aid of said first series of clock pulses a signal having a frequency equal to b(n+1) times the clock pulse rate in said first series, wherein b is a positive number; and second means connected to said first generating means for generating with the aid of said signal a series of clock pulses having a rate equal to 1/bn times said frequency.

Claim 20

An apparatus as claimed in claim 17, wherein: said means for generating a second stream of binary words include a first shift register for processing n bits, means for clOcking the first shift register with said first series of clock pulses, means for shifting each word in said first stream into said first shift register; said register means including a second shift register for processing (n+1) bits; said transferring means include means connected to said second generating means for determining a predetermined state of operation of said second generating means, means connected to said means for determining said predetermined state of operation and to said second shift register for enabling a broadside transfer of binary bits from said first register to said second register in response to each determination of said predetermined state of operation, and means connected to said first and second registers for effecting said broadside transfer; said parity determining means include means for determining during the transfer of bits of each shifted word whether the particular word has an even number or an odd number of binary bits of a predetermined kind; said parity bits providing means connected to said register means include means for providing each word in said second shift register with a first kind of parity bit when the particular word has an even number of binary bits of said predetermined kind, and with a second kind of parity bit when the particular word has an odd number of binary bits of said predetermined kind; and said means for shifting each binary word with parity bit include means connected to said second generating means for shifting each word with parity bit out of said second shift register with said series of clock pulses having a rate equal to 1/bn times said frequency.

Claim 21

An apparatus as claimed in claim 11, wherein said means for generating said second series of clock pulses include: first means for generating with the aid of said first series of clock pulses a first signal having a frequency equal to b(n+1) times the clock pulse rate in said first series, wherein b is a positive number; second means connected to said first means for generating with the aid of said first signal a second signal having a pulse rate equal to 1/(b(n+1)) times the frequency of said first signal; third means connected to said first and second generating means for assisting with said second signal the generation of said first signal by said first generating means; fourth means connected to said first means for generating with the aid of said first signal a third signal having a pulse rate equal to 1/bn times the frequency of said first signal.

Claim 22

An apparatus as claimed in claim 19, wherein: said means for generating a second stream of binary words include a first shift register for processing n bits, means connected to said first shift register for clocking said first shift register with said first series of clock pulses, means connected to said first shift register for shifting each word in said first stream into said first shift register; said register means include a second shift register for processing (n+1) bits; said transferring means include means for transferring the bits in each word from the first shift register to the second shift register; said parity determining means include parity generator means connected to said first and second shift registers and including means for determining whether words have an even number or an odd number of binary ones; and said parity bits providing means connected to said register means include means for applying to said second register a binary one as a parity bit in response to a determination that a binary word has an even number of binary ones.

Claim 23

An apparatus as claimed in claim 20, wherein: said second means include a seven counter; and said fourth means include an eight counter.

Claim 24

An apparatus as claimed in claim 21, wherein said means for transferring bits in each word from the first shift register to the seconD shift register include: means connected to said second and fourth means for determining a first predetermined count in said seven counter and a second predetermined count in said eight counter; and means connected to said second and fourth means and to said second shift register for enabling a broadside transfer of binary bits from said first register to said second register in response to each determination of said first and second counts.

Claim 25

An apparatus as claimed in claim 20, wherein said first generating means include: a phase detector having a first input for receiving said first series of clock pulses, a second input for receiving said second signal, and an output for providing a signal corresponding to the frequency difference between said first series of clock pulses and said second signal; and means connected to said phase detector and including voltage controlled oscillator means for generating said first signal from said difference signal.

Claim 26

An apparatus as claimed in claim 23, wherein: said means for generating said first signal from said difference signal include amplifier means having a feedback circuit with low-pass filter means, and amplitude limiter means connected to said low-pass filter means for preventing spurious frequency locking by said voltage controlled oscillator means.

Claim 27

In apparatus for synchronizing bits of binary data, the improvement comprising in combination: means for receiving said bits; selectively actuable means connected to said bit receiving means for regenerating said received bits; phase lock loop means connected to said bit receiving means for generating clock pulses synchronized with said regenerated bits, said phase lock loop means including digital counter means for generating a phase reference signal in said phase lock loop means; and means connected to said phase lock loop means for actuating said bit regenerating means during the occurrence of a center portion of each received bit and in response to said generated clock pulses and a predetermined counting state of said digital counter means.

Claim 28

In apparatus for synchronizing bits of binary data, the improvement comprising in combination: means for receiving said bits; selectively actuable means connected to said bit receiving means for regenerating said received bits; phase lock loop means connected to said bit receiving means for generating clock pulses synchronized with said regenerated bits, said phase lock loop means including digital counter means for generating a phase reference signal in said phase lock loop means; and means connected to said phase lock loop means for actuating said bit regenerating means during the occurrence of a center portion of each received bit and in response to said generated clock pulses and a predetermined counting state of said digital counter means.

Claim 29

An apparatus as claimed in claim 25, wherein: said bit receiving means include means for detecting signal level edges in said received bits, means connected to said edge detecting means for generating constant time pulses in response to detected signal level edges, and means for applying said constant time pulses to said phase lock loop means.

Claim 30

An apparatus as claimed in claim 26, wherein: said edge detecting means include first means for providing first changing signal levels in response to received bit edges, second means for providing second changing signal levels in response to received bit edges, said second means including third means for delaying said second changing signal levels relative to said first changing signal levels, and fourth means connected to said first and second means for providing edge indicative pulses in delay intervals between said first and second changing signal levels; and said contant time pulse generating means include means for generating a constant time pulse in response to each edge indicative pulse.

Claim 31

An apparatus as claimed in claim 26, wherein: said phase lock loop means include phase detector means for providing an error signal in response to a comparison of the phases of said generated constant time pulses and of said phase reference signal, voltage controlled oscillator means for generating said clock pulses, loop filter means for applying said error signal to said voltage controlled oscillator, and means for clocking said digital counter means with said clock pulses.

Claim 32

In apparatus for synchronizing and modifying binary data, the improvement comprising in combination: means for receiving said bits; selectively actuable means connected to said bit receiving means for regenerating said received bits; means connected to said regenerating means for modifying said regenerated bitS; phase lock loop means connected to said bit receiving means for generating first clock pulses synchronized with said regenerated bits, said phase lock loop means including digital counter means for generating a phase reference signal in said phase lock loop and for operating said bit modifying means; means connected to said phase lock loop means for actuating said bit regenerating means during the occurrence of a center portion of each received bit in response to said generated first clock pulses and a predetermined counting state of said digital counter means; and means connected to said phase lock loop means for generating second clock pulses synchronized with said modified bits.

Claim 33

In apparatus for synchronizing and modifying binary data, the improvement comprising in combination: means for receiving said bits; selectively actuable means connected to said bit receiving means for regenerating said received bits; means connected to said regenerating means for modifying said regenerated bitS; phase lock loop means connected to said bit receiving means for generating first clock pulses synchronized with said regenerated bits, said phase lock loop means including digital counter means for generating a phase reference signal in said phase lock loop and for operating said bit modifying means; means connected to said phase lock loop means for actuating said bit regenerating means during the occurrence of a center portion of each received bit in response to said generated first clock pulses and a predetermined counting state of said digital counter means; and means connected to said phase lock loop means for generating second clock pulses synchronized with said modified bits.

Claim 34

An apparatus as claimed in claim 29, wherein: said bit modifying means include first register means for shifting said regenerated bits at a first clock rate, and means connected to said digital counter means for clocking said first register means; and said bit modifying means further include second register means connected to said first register means for shifting at least part of said shifted bits at a second clock rate different from said first clock rate; and said means for generating second clock pulses include further digital counter means connected between said phase lock loop means and said second register means for clocking said second register means and for providing said second clock pulses.

Claim 35

An apparatus as claimed in claim 30, wherein: said bit receiving means include means for detecting signal level edges in said received bits, means connected to said edge detecting means for generating constant time pulses in response to detected signal level edges, and means for applying said constant time pulses to said phase lock loop means.

Claim 36

An apparatus as claimed in claim 30, wherein: said phase lock loop means include phase detector means for providing an error signal in response to a comparison of the phases of said generated constant time pulses and of said phase reference signal, voltage controlled oscillator means for generating said clock pulses, loop filter means for applying said error signal to said voltage controlled oscillator, and means for clocking said digital counter means with said clock pulses.

Claim 37

In apparatus for synchronizing and removing parity bits from binary words including parity bits, the improvement comprising in combination: means for receiving said bits including parity bits; selectively actuable means connected to said bit receiving means for regenerating said received bits including said parity bits; means connected to said bit regenerating means for identifying parity bits in said regenerated bits; means for removing identified parity bits from said regenerated bits; means connected to said removing means for expanding said regenerated bits from which parity bits have been removed into the time periods of the removed parity bits; phase lock loop means connected to said bit receiving means for generating first clock pulses synchronized with said regenerated bits including said parity bits, said phase lock loop means including digital counter means for generating a phase reference signal in said phase lock loop and for operating said parity bit identifying means; means connected to said phase lock loop means for actuating said bit regenerating means in response to said generated clock pulses and a predetermined counting state of said digital counting means; and means connected to said phase lock loop means for operating said expanding means and for generating second clock pulses synchronized with said expanded bits.

Claim 38

In apparatus for synchronizing and removing parity bits from binary words including parity bits, the improvement comprising in combination: means for receiving said bits including parity bits; selectively actuable means connected to said bit receiving means for regenerating said received bits including said parity bits; means connected to said bit regenerating means for identifying parity bits in said regenerated bits; means for removing identified parity bits from said regenerated bits; means connected to said removing means for expanding said regenerated bits from which parity bits have been removed into the time periods of the removed parity bits; phase lock loop means connected to said bit receiving means for generating first clock pulses synchronized with said regenerated bits including said parity bits, said phase lock loop means including digital counter means for generating a phase reference signal in said phase lock loop and for operating said parity bit identifying means; means connected to said phase lock loop means for actuating said bit regenerating means in response to said generated clock pulses and a predetermined counting state of said digital counting means; and means connected to said phase lock loop means for operating said expanding means and for generating second clock pulses synchronized with said expanded bits.

Claim 39

An apparatus as claimed in claim 33, wherein: said means for actuating said bit regenerating means include means for actuating said bit regenerating means only during the occurrence of a center portion of each received bit.

Claim 40

An apparatus as claimed in claim 33, wherein: said means for operating said expanding means and fOr generating said second clock pulses include further digital counter means connected between said phase lock loop means and said expanding means.

Claim 41

An apparatus as claimed in claim 33, wherein: said parity bit identifying means include means for determining for m(n+p) bits of said received bits whether the number of binary ''''one'''' bits in any set of (n+p) bits of said m(n+p) bits is even or odd, wherein m is a positive integer greater than one, n is the number of word bits in each of said binary words, and p is the number of parity bits in each of said binary words; and said parity bit removing means include means for transferring in response to said determination only n bits from each set of (n+p) bits of said m(n+p) bits.

Claim 42

An apparatus as claimed in claim 36, wherein: said parity bit identifying means include means for effecting said determination simultaneously for at least some sets of (n+p) bits of said m(n+p) bits.