US4799239A
Expired / Lapsed
US
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Phase-coherent FSK signal demodulator
Assignee: Kidde Inc
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Filing: 1986-04-28
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Granted: 1989-01-17
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Expires: 2006-04-28
Abstract
Abstract A system and process for receiving phase-coherent FSK signals having data and clock components which includes a plurality of subsystems and a means for carrying data among the subsystems. At least two of the subsystems are able to communicate by means of a transmitter in one of them and a receiver in the other. The receiver includes a demodulator for separating the data and clock components of the encoded phase-coherent FSK signals. The clock demodulator includes a first transition detector and a 90-degree phase shift circuit which both receive the encoded signal. A second transition detector receives the output of the phase shift or phase delay circuit. An OR gate receives the output of the first and second transition detectors to produce a four times clock signal. The data component of the phase-coherent FSK signal is recovered by either of two alternate circuits. The first circuit uses a shift register which examines at least four samples of data in conjunction with a pair of exclusive OR gates, a NOR gate, and a flip-flop. An alternate data component demodulator includes a first 90-degree phase delay circuit and an inverter both receiving the encoded data and transmitting it to a first exclusive OR gate. A second 90-degree phase delay circuit receives the output of the first exclusive OR gate. A second exclusive OR gate receives the outputs of both the second phase delay circuit and the first exclusive OR gate.
Inventors
- 👤 Sheldon Pearlman
- 👤 Anatoly Fridland
- 👤 Gunther J. Martin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:57
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/2335
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
135 words
A system for receiving phase-coherent FSK signals having data and clock components comprising: a plurality of subsystems; means for carrying the data among the subsystems; at least two of the subsystems being able to communicate by a means for transmitting and a means for receiving phase-coherent FSK signals in the subsystems; the means for receiving including demodulation means for the data and clock components, the clock component demodulation means including a plurality of operatively parallel connected transition detectors which generate signals when the entering phase-coherent FSK data changes states and when a phase-delayed wave of the phase-coherent FSK data changes state, wherein the clock component demodulation means includes a means for combining the outputs of the transition detectors and is operatively connected thereto to form a signal which is a multiple of the clock component.
Claim 2
Independent Claim
135 words
A system for receiving phase-coherent FSK signals having data and clock components comprising: a plurality of subsystems; means for carrying the data among the subsystems; at least two of the subsystems being able to communicate by a means for transmitting and a means for receiving phase-coherent FSK signals in the subsystems; the means for receiving including demodulation means for the data and clock components, the clock component demodulation means including a plurality of operatively parallel connected transition detectors which generate signals when the entering phase-coherent FSK data changes states and when a phase-delayed wave of the phase-coherent FSK data changes state, wherein the clock component demodulation means includes a means for combining the outputs of the transition detectors and is operatively connected thereto to form a signal which is a multiple of the clock component.
Claim 3
Dependent Claim
37 words
The system for receiving phase-coherent FSK signals of claim 1, wherein the clock component demodulation means and transition detectors include a first transistion detector receiving encoded data and a 90-degree phase-delay means receiving the same encoded data.
Claim 4
Dependent Claim
50 words
The system for receiving phase-coherent FSK signals of claim 2, wherein the clock component demodulation means includes a second transition detector which receives the output of the 90-degree phase delay, and the outputs of the first and second transition detectors are the input to the means for combining the outputs.
Claim 5
Dependent Claim
50 words
The system for receiving phase-coherent FSK signals of claim 3, wherein the means for combining is an OR gate which receives the signals from the transition detectors and converts them to a signal which is four times the clock component of the incoming encoded signal to the means for receiving.
Claim 6
Dependent Claim
36 words
The system for receiving phase-coherent FSK signals of claim 4, wherein the phase-coherent FSK signal shift frequencies have one frequency equal to the clock period of the data and the second frequency at twice this clock.
Claim 7
Dependent Claim
66 words
The system for receiving phase-coherent FSK signals of claim 1, wherein the means for receiving includes a demodulation means for the data component of the encoded phase-coherent FSK signals, the data component demodulation means including a means for phase-delaying the phase-coherent FSK signal and means for comparing the incoming encoded phase-coherent FSK signal in a non-iterative fashion to generate a signal indicative of the data component.
Claim 8
Dependent Claim
101 words
The system for receiving phase-coherent FSK signals of claim 6, wherein the data component demodulation means includes a shift register having a capacity to contain at least four bits of data, the shift register having an input of the encoded data and the clock pulse so that the input to the shift register is the encoded phase-coherent FSK signal and a series of phase-delayed signals of the incoming encoded phase-coherent FSK signal and means for comparing the input signals to the shift register to generate a signal indicative of the data component of the phase-coherent FSK signal or its inverted signal.
Claim 9
Dependent Claim
35 words
The system for receiving phase-coherent FSK signals of claim 7, wherein the data component demodulation means includes at least two exclusive OR gates receiving the output of the shift register and being operatively connected thereto.
Claim 10
Dependent Claim
33 words
The system for receiving phase-coherent FSK signals of claim 8, wherein the data component demodulation means includes a NOR gate operatively connected to the two exclusive OR gates and receiving the output thereof.
Claim 11
Dependent Claim
45 words
The system for receiving phase-coherent FSK signals of claim 9, wherein the data component demodulator further includes a flip-flop operatively attached to and receiving the output from the NOR gate and a clock signal as its input and generating a signal which is the data.
Claim 12
Dependent Claim
63 words
The system for receiving phase-coherent FSK signals of claim 6, wherein the data component demodulations means includes a first 90-degree phase delay means, an inverter, and a first exclusive OR gate operatively connected so that the encoded data is the input to the first 90-degree phase delay means and the inverter and their outputs are the input of the first exclusive OR gate.
Claim 13
Dependent Claim
74 words
The system for receiving phase-coherent FSK signals of claim 11, wherein the data component demodulation means further includes a second 90-degree phase delay means and a second exclusive OR gate operatively connected so that the output of the first exclusive OR gate is the input to the second 90-degree phase delay means and the input to the second exclusive OR gate and the output of the second exclusive OR gate is the data component.
Claim 14
Dependent Claim
113 words
A process for demodulating an encoded phase-coherent FSK signal having data and clock components in a system having a plurality of subsystems and means for carrying signals among them, comprising: transmitting a phase-coherent FSK signal from one subsystem to a second subsystem; detecting the transitions of the phase-coherent FSK signal and generating a first set of transition signals; detecting the transitions of the phase-coherent FSK signal after it has been phase-delayed and generating a second set of transition signals; and combining the first and second sets of transition signals to generate a representative clock pulse of the phase-coherent FSK signal, wherein the phase-coherent FSK signal is delayed 90 degrees of the lowest frequency.
Claim 15
Dependent Claim
113 words
A process for demodulating an encoded phase-coherent FSK signal having data and clock components in a system having a plurality of subsystems and means for carrying signals among them, comprising: transmitting a phase-coherent FSK signal from one subsystem to a second subsystem; detecting the transitions of the phase-coherent FSK signal and generating a first set of transition signals; detecting the transitions of the phase-coherent FSK signal after it has been phase-delayed and generating a second set of transition signals; and combining the first and second sets of transition signals to generate a representative clock pulse of the phase-coherent FSK signal, wherein the phase-coherent FSK signal is delayed 90 degrees of the lowest frequency.
Claim 16
Dependent Claim
27 words
The process of claim 13, wherein the first and second sets of transition signals are added to produce a signal that is four times the clock signal.
Claim 17
Dependent Claim
44 words
The process of claim 14, wherein in order to produce the data component of the encoded phase-coherent FSK signal, the signal is sampled at least four times per bit period, each sample being taken after the previous sample has been phase-delayed by 90 degrees.
Claim 18
Dependent Claim
34 words
The process of claim 15, wherein the four samples are compared by passing the first two samples through a first exclusive OR gate and the second two samples through a second exclusive OR gate.
Claim 19
Dependent Claim
21 words
The process of claim 16, wherein the outputs of the first and second OR gates are passed through a NOR gate.
Claim 20
Dependent Claim
36 words
The process of claim 17, wherein the output of the NOR gate is passed through a flip-flop which also has the clock pulse as an input whereby the data component of the phase-coherent FSK is produced.
Claim 21
Dependent Claim
28 words
The process of claim 13, wherein the encoded data is delayed 90 degrees and inverted, and the two resulting signals are transmitted to a first exclusive OR gate.
Claim 22
Dependent Claim
60 words
The process of claim 19, wherein the output of the first exclusive OR gate is delayed 90 degrees and the output of the first exclusive OR gate and delayed output of the first exclusive OR gate are passed into a second exclusive OR gate which gives an output signal which is the data component of the encoded phase-coherent FSK signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-17 | 1992-07-18 | 1993-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-17 | 1996-07-18 | 1997-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-17 | 2000-07-18 | 2001-01-17 | $7700.00 | Window Closed / Lapsed |