Patent US3139487A successfully refreshed from Google Patents.
US3962647A
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Biphase waveform generator using shift registers
Assignee: Bendix Corp
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Filing: 1974-09-27
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Granted: 1976-06-08
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Expires: 1994-09-27
Abstract
Abstract A biphase waveform is generated using a serial register of length 2N where N is the number of bits to be transmitted. Each data bit is loaded into a shift register, both directly and through an inverter. Double speed clocking provides an alternating logic level signal for each data bit and the phases of the alternating signals are combined to provide the biphase waveform.
Inventors
- 👤 Jay L. Richman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:56
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
103 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits; means for applying the data bits to the register including a plurality of inverters and means for applying each of the data bits to the register directly and through a corresponding inverter; means for clocking the register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; and means for combining the phases of the alternating signals for each data bit to provide the biphase waveform.
Claim 2
Dependent Claim
103 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits; means for applying the data bits to the register including a plurality of inverters and means for applying each of the data bits to the register directly and through a corresponding inverter; means for clocking the register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; and means for combining the phases of the alternating signals for each data bit to provide the biphase waveform.
Claim 3
Independent Claim
86 words
A method for generating a biphase waveform from a plurality of data bits, including the steps of: applying the data bits to a serial register of length 2N where N is the number of data bits; clocking the register at twice an output data rate for enabling the register to provide an alternating logic level signal for each data bit; and combining the phases of the alternating signals for each data bit for providing the biphase waveform including enveloping the alternating signals with an enabling signal.
Claim 4
Independent Claim
86 words
A method for generating a biphase waveform from a plurality of data bits, including the steps of: applying the data bits to a serial register of length 2N where N is the number of data bits; clocking the register at twice an output data rate for enabling the register to provide an alternating logic level signal for each data bit; and combining the phases of the alternating signals for each data bit for providing the biphase waveform including enveloping the alternating signals with an enabling signal.
Claim 5
Dependent Claim
107 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits; means for applying the data bits to the register; means for clocking the register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; and means for combining the phases of the alternating signals for each data bit to provide the biphase waveform including a NOR gate connected to the register and responsive to the alternating logic level signals, and responsive to an enabling pulse for providing the biphase waveform.
Claim 6
Dependent Claim
107 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits; means for applying the data bits to the register; means for clocking the register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; and means for combining the phases of the alternating signals for each data bit to provide the biphase waveform including a NOR gate connected to the register and responsive to the alternating logic level signals, and responsive to an enabling pulse for providing the biphase waveform.
Claim 7
Dependent Claim
184 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits, including at least a first register and a second register following the first register; means for applying the data bits to the serial register; means for clocking the serial register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; means for combining the phases of the alternating signals for each data bit to provide the biphase waveform; each of the first and second registers having a load terminal, an input terminal, a clock terminal, data bit terminals, an output terminal and a complementary output terminal; and a load word is applied to the load terminals, the data bits are applied to the data bit terminals, the clocking means is connected to the clock terminals, the output terminal of the first register is connected to the input terminal of the second register, and the complementary output terminal of the second register is connected to the combining means.
Claim 8
Dependent Claim
184 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits, including at least a first register and a second register following the first register; means for applying the data bits to the serial register; means for clocking the serial register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; means for combining the phases of the alternating signals for each data bit to provide the biphase waveform; each of the first and second registers having a load terminal, an input terminal, a clock terminal, data bit terminals, an output terminal and a complementary output terminal; and a load word is applied to the load terminals, the data bits are applied to the data bit terminals, the clocking means is connected to the clock terminals, the output terminal of the first register is connected to the input terminal of the second register, and the complementary output terminal of the second register is connected to the combining means.
Claim 9
Dependent Claim
131 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits; means for applying the data bits to the register; means for clocking the register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; means for combining the phases of the alternating signals for each data bit to provide the biphase waveform; certain of the data bits being predetermined so as to define a sync field and the register having corresponding predetermined data bit terminals; and certain of the predetermined register data bit terminals being connected to ground while the other of said terminals are connected through a load register to a power supply.
Claim 10
Dependent Claim
131 words
Apparatus for generating a biphase waveform from a plurality of data bits, comprising: a serial register of length 2N, where N is the number of data bits; means for applying the data bits to the register; means for clocking the register at twice a predetermined output data rate, with the register providing an alternating logic level signal for each data bit; means for combining the phases of the alternating signals for each data bit to provide the biphase waveform; certain of the data bits being predetermined so as to define a sync field and the register having corresponding predetermined data bit terminals; and certain of the predetermined register data bit terminals being connected to ground while the other of said terminals are connected through a load register to a power supply.
Claim 11
Independent Claim
97 words
A method for generating a biphase waveform from a plurality of data bits, including the steps of: applying the data bits to a serial register of length 2N where N is the number of data bits including applying the data bits directly to the register, inverting the bits, and applying the inverted bits to the register; clocking the register at twice an output data rate for enabling the register to provide an alternating logic level signal for each data bit; and combining the phases of the alternating signals for each data bit for providing the biphase waveform.
Claim 12
Independent Claim
97 words
A method for generating a biphase waveform from a plurality of data bits, including the steps of: applying the data bits to a serial register of length 2N where N is the number of data bits including applying the data bits directly to the register, inverting the bits, and applying the inverted bits to the register; clocking the register at twice an output data rate for enabling the register to provide an alternating logic level signal for each data bit; and combining the phases of the alternating signals for each data bit for providing the biphase waveform.
Claim 13
Independent Claim
124 words
A method for generating a biphase waveform from a plurality of data bits, including the steps of: applying the data bits to a serial register of length 2N where N is the number of data bits including predetermining certain of the data bits, said predetermined bits defining a sync field, predetermining certain corresponding register data bit terminals, connecting certain of the predetermined data bit terminals to ground, and connecting the other of said data bit terminals through a register to a power supply; clocking the register at twice an output data rate for enabling the register to provide an alternating logic level signal for each data bit; and combining the phases of the alternating signals for each data bit for providing the biphase waveform.
Claim 14
Independent Claim
124 words
A method for generating a biphase waveform from a plurality of data bits, including the steps of: applying the data bits to a serial register of length 2N where N is the number of data bits including predetermining certain of the data bits, said predetermined bits defining a sync field, predetermining certain corresponding register data bit terminals, connecting certain of the predetermined data bit terminals to ground, and connecting the other of said data bit terminals through a register to a power supply; clocking the register at twice an output data rate for enabling the register to provide an alternating logic level signal for each data bit; and combining the phases of the alternating signals for each data bit for providing the biphase waveform.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-08 | 1979-12-08 | 1980-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-08 | 1983-12-08 | 1984-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-08 | 1987-12-08 | 1988-06-08 | $7700.00 | Window Closed / Lapsed |