Refresh sampling built-in self test and repair circuit

Claim 3

The method of claim 1, wherein said determining failure times for cells in a first subset of the memory array comprises determining a first failure time for a first cell in the subset, wherein said determining a first failure time for a first cell in the subset comprises: writing said first cell with a first logical value; pausing for a first time interval; reading said first cell to obtain a first returned value; and examining said first returned value to determine whether said first cell has retained said first logical value; repeatedly performing said writing, pausing, reading, and examining of said first cell with changing values of said first time interval; detecting a first value of said first time interval which indicates a transition between retention and non-retention of said first logical value in said first cell; and assigning said first value to be the first failure time for said first cell.

Claim 4

The method of claim 2, wherein said determining failure times for cells in a subset of the memory array further comprises determining a second failure time for a second cell in the subset prior to said determining said first failure time for the first cell in the subset, wherein said determining said first failure time for the first cell further comprises initializing the first time interval to the second failure time prior to a first iteration of said repeatedly performing said writing, pausing, reading, and examining of said first cell.

Claim 5

The method of claim 2, wherein said repeatedly performing said writing, pausing, reading, and examining includes: increasing said first time interval if said examining determines that said first returned value is equal to said first logical value; and decreasing said first time interval if said examining determines that said first returned value is not equal to said first logical value.

Claim 6

The method of claim 1, wherein said calculating one or more statistical parameters based on said failure times includes calculating an average failure time for said cells in said first subset of the memory array.

Claim 7

The method of claim 5, wherein said determining a first refresh pause time comprises multiplying said average failure time by a scaling constant.

Claim 8

The method of claim 5, wherein said calculating one or more statistical parameters based one said failure times further includes calculating a standard deviation for the failure times.

Claim 9

The method of claim 7, wherein said determining a first refresh pause time comprises evaluating the expression AVG-k*STDEV, where k is a positive constant, AVG is the average failure time, and STDEV is the standard deviation of the failure times.

Claim 10

The method of claim 1, wherein said determining failure times for cells in said first subset, said calculating one or more statistical parameters, said determining a first refresh pause time, and said applying a data retention test to the memory array are performed in response to power being applied to the memory device.

Claim 11

The method of claim 1 further comprising waiting until said memory array attains a predetermined operational temperature, wherein said waiting is performed prior to said determining failure times for cells in said first subset of the memory array.

Claim 12

The method of claim 1, wherein said determining failure times for cells in said first subset, said calculating one or more statistical parameters, said determining a first refresh pause time, and said applying a data retention test to the memory array are performed in response to a command asserted by an operating system routine executing on a central processing unit coupled to the memory device.

Claim 13

The method of claim 1 further comprising mapping the address of the faulty cell to the address of a redundant memory cell comprised within said memory device.

Claim 16

The system of claim 13, wherein the parameter calculation unit includes a first adder/accumulator to maintain a first cumulative sum of said failure time, wherein said parameter calculation unit is configured to determine an average failure time from said first cumulative sum.

Claim 17

The system of claim 14, wherein the parameter calculation unit is configured to determine said first refresh pause time by multiplying said average failure time by a predetermined constant value.

Claim 18

The system of claim 14, wherein the parameter calculation unit further includes a second adder-accumulator to maintain a second cumulative sum of squares of said failure times, wherein said parameter calculation unit is configured to determine a standard deviation of failure time from said first cumulative sum and said second cumulative sum.

Claim 19

The system of claim 16, wherein the parameter calculation unit is configured to determine said first refresh pause time by evaluating the expression AVG-k*SIGMA, wherein AVG is the average failure time, and SIGMA is the standard deviation of said failure times, and k is a constant.

Claim 20

The system of claim 13 further comprising: a plurality of redundant memory cells included within said memory array; a repair module coupled to receive a first address of a first faulty cell from said testing unit, and configured to store the first address of the first faulty cell and to associate said first address with a second address of one of said plurality of redundant memory cells; wherein said repair module is configured to intercept accesses to said first faulty cell and to reroute said accesses to said one of said plurality of redundant memory cells.

Claim 21

The system of claim 13, wherein said testing unit is configured to write a first logical value to a first cell, to pause for a first time interval, to read said first cell to obtain a first returned value, wherein said testing unit includes a first comparator for comparing said first returned value with said first logical value, wherein an output of said first comparator indicates whether said first cell has retained said first logical value.

Claim 22

The system of claim 19, wherein said testing unit is configured to repeat said writing, pausing, and reading of said first cell using changing values of said first time interval, wherein said testing unit is further configured to detect a first value of said first time interval which indicates a transition between retention and non-retention of said first logical value, and wherein said testing unit is configured to provide said first value to said parameter calculation unit as a first failure time for said first cell.

Claim 23

The system of claim 20, wherein said testing unit includes a first register for determining the length of said first time interval.

Claim 24

The system of claim 21, wherein said testing unit is configured to increment said first register when the output of said first comparator indicates that said first returned value is equal to said first logical value, and to decrement said first register when the output of said first comparator indicates that said first returned value is not equal to said first logical value.

Claim 25

The system of claim 20, wherein said testing unit includes a second register for storing the output of said first comparator from a first iteration of said repeated writing, pausing, and reading.

Claim 26

The system of claim 23, wherein said testing unit is configured to compare the output of said first comparator with the value of said second register after each iteration of said repeated writing, pausing, and reading, wherein a disagreement between said output of said first comparator and the value of said second register indicates said transition between retention and non-retention of said first logical value.

Claim 27

The system of claim 13, wherein said memory array includes a first weak write circuit coupled to said testing unit through a data line, wherein said first weak write circuit is configured to selectively couple said data line to one or more of said plurality of memory cells through either a direct path or a resistively loaded path in response to a weak enable input provided by said testing unit; wherein said testing unit is operable to control said weak enable input to select the resistively loaded path for write accesses during a first phase wherein said testing unit determines said failure times for said first subset of cells, and during a second phase wherein said testing unit detects faulty cells among said plurality of memory cells; and wherein said testing unit is operable to control said weak enable input to select the direct path when said testing unit performs read accesses to said memory array.

Claim 28

A memory device comprising: a plurality of memory cells; a data line; a first weak write circuit coupled to said data line and one or more cells of said plurality of memory cells, wherein said first weak write circuit includes: a first gating device coupled to said data line and said one or more cells; a resistive device coupled to said data line; a second gating device coupled to said resistive device and said one or more cells; and a weak enable line coupled to a first control input of said first gating device and to a second control input of said second gating device; wherein said first gating device is configured to couple said data line to said one or more cells when a first logical value is asserted on said weak enable line; wherein said second gating device is configured to decouple said resistive device from said one or more cells when said first logical value is asserted on said weak enable line; wherein said first gating device is configured to decouple said data line from said one or more cells when a second logical value is asserted on said weak enable line; and wherein said second gating device is configured to couple said resistive device to said one or more cells when said second logical value is asserted on said weak enable line; wherein said second logical value is the complement of said first logical value.

Claim 29

A memory device comprising: a plurality of memory cells; a data line; a first weak write circuit coupled to said data line and one or more cells of said plurality of memory cells, wherein said first weak write circuit includes: a first gating device coupled to said data line and said one or more cells; a resistive device coupled to said data line; a second gating device coupled to said resistive device and said one or more cells; and a weak enable line coupled to a first control input of said first gating device and to a second control input of said second gating device; wherein said first gating device is configured to couple said data line to said one or more cells when a first logical value is asserted on said weak enable line; wherein said second gating device is configured to decouple said resistive device from said one or more cells when said first logical value is asserted on said weak enable line; wherein said first gating device is configured to decouple said data line from said one or more cells when a second logical value is asserted on said weak enable line; and wherein said second gating device is configured to couple said resistive device to said one or more cells when said second logical value is asserted on said weak enable line; wherein said second logical value is the complement of said first logical value.

Claim 30

The system of claim 26, wherein said resistive device is a polysilicon resistor.

Claim 31

The system of claim 26, wherein said first gating device is an n-channel transistor, and wherein said first control input is the gate of said n-channel transistor.

Claim 32

The system of claim 26, wherein said second gating device is a p-channel transistor, and wherein said second control input is the gate of said p-channel transistor.