System for generating a variable signal in response to a toggle signal selectively delayed using a clock edge and time delay measured from the clock edge

Claim 2

A signal generating digital circuit, the circuit receiving a clock signal having clock edges including a first clock edge which is one of a rising edge and a falling edge and a second clock edge, which is one of a rising edge and a falling edge following the first clock edge without intervening clock edges, the clock signal having a clock period, comprising: a signal modifier for generating a resulting signal at a first signal state in response to and synchronized with the first clock edge, the resulting signal transitioning from the first signal state to a second signal state in response to a toggle signal; and a delay means, responsive to the clock signal and a time delay, for generating the toggle signal, the resulting signal at the first signal state having a duration that is other than a multiple of a half of the clock period and has a transition to the second signal state between two clock edges of the clock sigal entering the delay means, wherein the duration of the resulting signal at the first signal state that is responsive to and synchronized with the first clock edge is greater than the time measured between the first clock edge and the second clock edge; and the delay means generates the toggle signal in response to and synchronized with the second clock edge and the time delay is measured from the second clock edge.

Claim 3

The digital circuit of claim 1, wherein the first state corresponds to a logic 0 and the second state corresponds to a logic 1.

Claim 4

The digital circuit of claim 1, wherein the first state corresponds to a logic 1 and the second state corresponds to a logic 0.

Claim 5

The digital circuit of claim 2; wherein the signal modifier includes: a first enable means for receiving the clock signal and a first reset signal, the first reset signal having a first enabled state and a first disabled state, and for generating a first intermediate signal having one of the first signal state and the second signal state when the first reset signal is in the first disabled state; a second enable means for receiving the clock signal and a second reset signal, the second reset signal having a second enabled state and a second disabled state, and for generating a second intermediate signal having one of the first signal state and the second signal state when the second reset signal is in the second disabled state; and means, responsive to the first intermediate signal and the second intermediate signal, for generating the resulting signal.

Claim 6

The digital circuit of claim 4, wherein the toggle signal controls the first reset signal and the second reset signal to enable and disable the first enable means and the second enable means.

Claim 7

The digital circuit of claim 5, wherein the toggle signal includes a transition between a first toggle state and a second toggle state.

Claim 8

The digital circuit of claim 4, wherein the first enable means includes: a first flip-flop, including, a first data input for receiving a data valid signal, a first clock input for receiving the clock signal, a first reset input for receiving the first reset signal, and a first output for generating the first intermediate signal; and a first NOR gate, including, a plurality of inputs for receiving a test reset signal and the toggle signal, and a first NOR output for supplying the first reset signal to the first reset input of the first flip-flop.

Claim 9

The digital circuit of claim 7, wherein the second enable means includes: a second flip-flop, including, a second data input for receiving the data valid signal, a second clock input for receiving the clock signal, a second reset input for receiving the second reset signal, and a second output for generating the second intermediate signal; and a second NOR gate, including, a plurality of inputs for receiving a test reset signal and the toggle signal, and a second NOR output for supplying the second reset signal to the second reset input of the second flip-flop.

Claim 10

The digital circuit of claim 8, wherein the means for generating the resulting signal includes a NOR gate for receiving the first intermediate signal and the second intermediate signal and for generating the resulting signal.

Claim 11

The digital circuit of claim 9, wherein the delay means includes: a third NOR gate for receiving the second reset signal and the resulting signal and for generating a toggle control signal; a delay buffer for receiving the clock signal and for supplying a toggle clock signal; and a third flip-flop for receiving the toggle control signal and the toggle dock signal and for supplying the toggle signal to the first enable means and the second enable means.

Claim 12

The digital circuit of claim 1, wherein the signal is an output enable signal for an output enable circuit in a tri-state synchronous bus driver.

Claim 13

The digital circuit of claim 1, wherein the signal is a CAS signal for a column access strobe (CAS) generating circuit for a dynamic random access memory (DRAM) computing environment.

Claim 14

A signal generating digital circuit, the circuit receiving a clock signal having clock edges including a first clock edge which is one of a rising edge and a falling edge and a second clock edge which is one of a rising edge and a falling edge, the clock signal having a clock period, comprising: a signal modifier for generating a resulting signal at a first signal state in response to and synchronized with the first clock edge, the resulting signal transitioning from the first signal state to a second signal state in response to a toggle signal, wherein the signal modifier includes, a first enable means for receiving the clock signal and a first reset signal, the first reset signal having a first enabled state and a first disabled state, and for generating a first intermediate signal having one of the first signal state and the second signal state when the first reset signal is in the first disabled state, a second enable means for receiving the clock signal and a second reset signal, the second reset signal having a second enabled state and a second disabled state, and for generating a second intermediate signal having one of the first signal state and the second signal state when the second reset signal is in the second disabled state, and means, responsive to the first intermediate signal and the second intermediate signal, for generating the resulting signal; and a delay means, responsive to the second clock edge of the clock signal and a time delay, for generating the toggle signal, the resulting signal at the first signal state having a duration that is other than a multiple of a half of the clock period and has a transition to the second signal state between two clock edges of the clock signal entering the delay means.

Claim 15

A signal generating digital circuit, the circuit receiving a clock signal having clock edges including a first clock edge which is one of a rising edge and a falling edge and a second clock edge which is one of a rising edge and a falling edge, the clock signal having a clock period, comprising: a signal modifier for generating a resulting signal at a first signal state in response to and synchronized with the first clock edge, the resulting signal transitioning from the first signal state to a second signal state in response to a toggle signal, wherein the signal modifier includes, a first enable means for receiving the clock signal and a first reset signal, the first reset signal having a first enabled state and a first disabled state, and for generating a first intermediate signal having one of the first signal state and the second signal state when the first reset signal is in the first disabled state, a second enable means for receiving the clock signal and a second reset signal, the second reset signal having a second enabled state and a second disabled state, and for generating a second intermediate signal having one of the first signal state and the second signal state when the second reset signal is in the second disabled state, and means, responsive to the first intermediate signal and the second intermediate signal, for generating the resulting signal; and a delay means, responsive to the second clock edge of the clock signal and a time delay, for generating the toggle signal, the resulting signal at the first signal state having a duration that is other than a multiple of a half of the clock period and has a transition to the second signal state between two clock edges of the clock signal entering the delay means.

Claim 16

The digital circuit of claim 13, wherein the toggle signal controls the first reset signal and the second reset signal to enable and disable the first enable means and the second enable means.

Claim 17

The digital circuit of claim 14, wherein the toggle signal includes a transition between a first toggle state and a second toggle state.

Claim 18

The digital circuit of claim 13, wherein the first enable means includes: a first flip-flop, including, a first data input for receiving a data valid signal, a first clock input for receiving the clock signal, a first reset input for receiving the first reset signal, and a first output for generating the first intermediate signal; and a first NOR gate, including, a plurality of inputs for receiving a test reset signal and the toggle signal, and a first NOR output for supplying the first reset signal to the first reset input of the first flip-flop.

Claim 19

The digital circuit of claim 16; wherein the second enable means includes: a second flip-flop, including, a second data input for receiving the data valid signal, a second clock input for receiving the clock signal, a second reset input for receiving the second reset signal, and a second output for generating the second intermediate signal; and a second NOR gate, including, a plurality of inputs for receiving a test reset signal and the toggle signal, and a second NOR output for supplying the second reset signal to the second reset input of the second flip-flop.

Claim 20

The digital circuit of claim 17, wherein the means for generating the resulting signal, includes a NOR gate for receiving the first intermediate signal and the second intermediate signal and for generating the resulting signal.

Claim 21

The digital circuit of claim 18, wherein the delay means includes: a third NOR gate for receiving the second reset signal and the resulting signal and for generating a toggle control signal; a delay buffer for receiving the clock signal and for supplying a toggle clock signal; and a third flip-flop for receiving the toggle control signal and the toggle clock signal and for supplying the toggle signal to the first enable means and the second enable means.

Claim 24

The method of claim 20, wherein the step of forming the resulting signal at the first signal state includes: forming a first reset signal, the first reset signal having an enabled state and a disabled state; and forming a first intermediate signal having one of the first signal state and the second signal state when the first reset signal is in the disabled state to trigger the formation of the resulting signal.

Claim 25

The method of claim 21, wherein the step of forming the transision of the resulting signal to the second signal state includes: forming a second reset signal having an enabled state and a disabled state; and forming a second intermediate signal having one of the first signal state and the second signal state when the second reset signal is in the disabled state to trigger the formation of the resulting signal.