Semiconductor memory having writing and reading transistors, method of fabrication thereof, and method of use thereof

Abstract

Abstract Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench. Also disclosed is a method of operating the memory cell, wherein the voltage applied to the word line, in a standby condition, is intermediate to the voltage applied to the word line during the writing operation and during the reading operation.

Inventors

• 👤 Shuji Shukuri
• 👤 Toru Koga
• 👤 Shinichiro Kimura
• 👤 Digh Hisamoto
• 👤 Kazuhiko Sagara
• 👤 Tokuo Kure
• 👤 Eiji Takeda

Bibliographic Details