US4935896A
Expired / Lapsed
US
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Semiconductor memory device having three-transistor type memory cells structure without additional gates
Assignee: Mitsubishi Electric Corp
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Filing: 1988-11-02
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Granted: 1990-06-19
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Expires: 2008-11-02
Abstract
Abstract A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.
Inventors
- 👤 Tetsuya Matsumura
- 👤 Masahiko Yoshimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:12
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/406; G11C7/067
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
254 words
A semiconductor memory device comprising: a plurality of memory cells (10) arranged in at least one column for storing information, at least one pair of write bit lines, (WB1, WB2) provided corresponding to each of said at least one column of said plurality of memory cells (10) for writing information to said plurality of memory cells (10), at least one read bit line (RB) provided corresponding to each of said at least one column of said plurality of memory cells (10) for reading out information stored in said plurality of memory cells (10), a plurality of first selecting lines (WWL) provided corresponding to each of said memory cells (10) in each said column, a plurality of second selecting lines (RWL) provided corresponding to each of said memory cells (10) in each said column, first selecting means (62; 72) for applying a first selecting signal to any of said plurality of first selecting lines (WWL), and second selecting means (63; 73) for applying a second selecting signal to any of said plurality of second selecting lines (RWL), of each of said memory cells (10) comprising: first means (3) for storing an information signal; second means (1) responsive to said first selecting signal for transferring an information signal from either one of said pair of write bit lines (WB1, WB2) to said first means (3) to be stored therein; and third means (2) responsive to said second selecting signal for transferring said information signal stored in said first means (3) to said read bit line (RB).
Claim 2
Dependent Claim
254 words
A semiconductor memory device comprising: a plurality of memory cells (10) arranged in at least one column for storing information, at least one pair of write bit lines, (WB1, WB2) provided corresponding to each of said at least one column of said plurality of memory cells (10) for writing information to said plurality of memory cells (10), at least one read bit line (RB) provided corresponding to each of said at least one column of said plurality of memory cells (10) for reading out information stored in said plurality of memory cells (10), a plurality of first selecting lines (WWL) provided corresponding to each of said memory cells (10) in each said column, a plurality of second selecting lines (RWL) provided corresponding to each of said memory cells (10) in each said column, first selecting means (62; 72) for applying a first selecting signal to any of said plurality of first selecting lines (WWL), and second selecting means (63; 73) for applying a second selecting signal to any of said plurality of second selecting lines (RWL), of each of said memory cells (10) comprising: first means (3) for storing an information signal; second means (1) responsive to said first selecting signal for transferring an information signal from either one of said pair of write bit lines (WB1, WB2) to said first means (3) to be stored therein; and third means (2) responsive to said second selecting signal for transferring said information signal stored in said first means (3) to said read bit line (RB).
Claim 3
Dependent Claim
131 words
A semiconductor memory device according to claim 1, wherein said first means comprises a first transistor (3) for storing information, said second means comprises a second transistor (1) connected between either one of said pair of write bit lines (WB1, WB2) and said first transistor (3) and responsive to said first selecting signal applied to said first selecting lines (WWL) for transferring to said first transistor (3) information applied through said one of said pair of write bit lines (WB1, WB2), and said third means comprises a third transistor (2) connected between said read bit line (RB) and said first transistor (3) and responsive to said second selecting signal applied to said second selecting line (RWL) for transferring information stored in said first transistor (3) to said read bit line (RB).
Claim 4
Dependent Claim
115 words
A semiconductor memory device according to claim 2, wherein said first transistor (3) comprises one conduction terminal coupled to a predetermined potential, another conduction terminal and a control terminal, said second transistor (1) comprises one conduction terminal connected either one of said pair of write bit lines (WB1, WB2) , another conduction terminal connected to said control terminal in said first transistor (3) and a control terminal connected to said first selecting lines (WWL), and said third transistor (2) comprises one conduction terminal connected to said read bit line (RB), another conduction terminal connected to said other conduction terminal in said first transistor (3) and a control terminal connected to said second selecting lines (RWL).
Claim 5
Dependent Claim
28 words
A semiconductor memory device according to claim 3, wherein said first transistor (3), said second transistor (1) and said third transistor (2) comprise an MOS field effect transistor.
Claim 6
Dependent Claim
60 words
A semiconductor memory device according to claim 1, wherein said first selecting means comprises first sequentially selecting means (62) for applying sequentially said first selecting signal to said plurality of first selecting lines (WWL), and said second selecting means comprises second sequentially selecting means (63) for applying sequentially said second selecting signal to said plurality of second selecting lines (RWL).
Claim 7
Dependent Claim
26 words
A semiconductor memory device according to claim 5, wherein said first sequentially selecting means and said second sequentially selecting means comprise a ring pointer (62, 63).
Claim 8
Dependent Claim
40 words
A semiconductor memory device according to claim 6, which further comprises a refreshing sense amplifier (30) connected to each of said pairs of write bit lines (WB1, WB2) for amplifying information on the pair of write bit lines (WB1, WB2).
Claim 9
Dependent Claim
63 words
A semiconductor memory device according to claim 1, wherein memory cells in odd numbers of memory cells (10) in each said column are connected to one of said pair of write bit lines (WB1, WB2), and memory cells in even numbers of memory cells (10) in each said column are connected to the other of said pair of write bit lines (WB1, WB2).
Claim 10
Dependent Claim
27 words
A semiconductor memory device according to claim 1, which further comprises a write driver (20) connected to each of said pairs of write bit lines (WB1, WB2).
Claim 11
Dependent Claim
72 words
A semiconductor memory device according to claim 1, wherein said first selecting means comprises a first decoder (72) responsive to a first address signal externally applied for applying said first selecting signal to any of said first selecting lines (WWL), and said second selecting means comprises a second decoder (73) responsive to a second address signal externally applied for applying said second selecting signal to any of said second selecting lines (RWL).
Claim 12
Dependent Claim
40 words
A method of accessing according to claim 10, wherein said first selecting signal is applied sequentially to said plurality of first selecting lines (WWL), and said second selecting signal is applied sequentially to said plurality of second selecting lines (RWL).
Claim 13
Dependent Claim
56 words
A method of accessing according to claim 10, wherein said first selecting signal is applied to any of said first selecting liens (WWL) in response to said first address signal externally applied, and said second selecting signal is applied to any of said second selecting lines (RWL) in response to a second address signal externally applied.
Claim 14
Independent Claim
322 words
A method of accessing a semiconductor memory, said device comprising: a plurality of memory cells (10) arranged in at least one column for storing information, at least one pair of write bit lines (WB1, WB2) provided corresponding to each column of said plurality of memory cells (10) for writing information to said plurality of memory cells (10), at least one read bit line (RB) provided corresponding to each column of said plurality of memory cells (10) for reading out information stored in said plurality of memory cells (10), a plurality of first selecting lines (WWL) provided corresponding to each of said memory cells (10) in each said column, a plurality of second selecting lines (RWL) provided corresponding to each of said memory cells (10) in each said column, first selecting means (62; 72) for generating a first selecting signal, second selecting means (63; 73) for generating a second selecting signal, each of said memory cells (10) comprising: a first transistor (3) for storing information, a second transistor (1) connected between either one of said pair of write bit lines (WB1, WB2) and said first transistor (3) and responsive to said first selecting signal applied to said first selecting lines (WWL) for transferring to said first transistor (3) information applied through said one of said pair of write bit lines (WB1, WB2), and a third transistor (2) connected between said read bit line (RB) and said first transistor (3) and responsive to said second selecting signal applied to said second selecting line (RWL) for transferring information stored in said first transistor (3) to said read bit line (RB), a method of accessing to said memory cell (10) comprising: applying a first selecting signal from said first selecting means (62; 72) to any of said plurality of first selecting lines (WWL), and applying a second selecting signal from said second selecting means (63; 73) to any of said plurality of second selecting lines (RWL).
Claim 15
Independent Claim
322 words
A method of accessing a semiconductor memory, said device comprising: a plurality of memory cells (10) arranged in at least one column for storing information, at least one pair of write bit lines (WB1, WB2) provided corresponding to each column of said plurality of memory cells (10) for writing information to said plurality of memory cells (10), at least one read bit line (RB) provided corresponding to each column of said plurality of memory cells (10) for reading out information stored in said plurality of memory cells (10), a plurality of first selecting lines (WWL) provided corresponding to each of said memory cells (10) in each said column, a plurality of second selecting lines (RWL) provided corresponding to each of said memory cells (10) in each said column, first selecting means (62; 72) for generating a first selecting signal, second selecting means (63; 73) for generating a second selecting signal, each of said memory cells (10) comprising: a first transistor (3) for storing information, a second transistor (1) connected between either one of said pair of write bit lines (WB1, WB2) and said first transistor (3) and responsive to said first selecting signal applied to said first selecting lines (WWL) for transferring to said first transistor (3) information applied through said one of said pair of write bit lines (WB1, WB2), and a third transistor (2) connected between said read bit line (RB) and said first transistor (3) and responsive to said second selecting signal applied to said second selecting line (RWL) for transferring information stored in said first transistor (3) to said read bit line (RB), a method of accessing to said memory cell (10) comprising: applying a first selecting signal from said first selecting means (62; 72) to any of said plurality of first selecting lines (WWL), and applying a second selecting signal from said second selecting means (63; 73) to any of said plurality of second selecting lines (RWL).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |