US4247919A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low power quasi-static storage cell
Assignee: Texas Instruments Inc
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Filing: 1979-06-15
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Granted: 1981-01-27
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Expires: 1999-06-15
Abstract
Abstract A semiconductor memory device forming a static type memory cell uses three field effect transistors. One is connected between a storage node and a bit line so it functions as an access transistor. The storage node is connected to a refresh node through a second transistor having its gate shorted to drain, and the third transistor connects the refresh node to a supply voltage. A voltage dependent capacitor connects the refresh node to a refresh clock. A logic 1 on the storage node turns on the third transistor and charges the refresh node, which turns on the capacitor so the refresh clock is coupled through to turn on the second transistor and refresh the storage node. When a logic 0 is stored, this will not happen.
Inventors
- 👤 Lionel S. White, Jr.
- 👤 Ngai H. Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/402; G11C11/4023; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
128 words
A static memory cell comprising first, second and third transistors each having a source-to-drain path and a gate, a source of logic voltages, a storage node, a refresh node, a voltage-dependent capacitor, a source of clock voltage, means connnecting the source of logic voltages to the storage node via the source-to-drain path of the first transistor, means connecting the storage node to the gate of the third transistor, means connecting the gate of the second transistor to the refresh node, the storage node being connected to the refresh node via the source-to-drain path of the second transistor, the source of clock voltage being connected to the refresh node via said capacitor, and a supply voltage connected to the refresh node via the source-to-drain path of the third transistor.
Claim 2
Dependent Claim
128 words
A static memory cell comprising first, second and third transistors each having a source-to-drain path and a gate, a source of logic voltages, a storage node, a refresh node, a voltage-dependent capacitor, a source of clock voltage, means connnecting the source of logic voltages to the storage node via the source-to-drain path of the first transistor, means connecting the storage node to the gate of the third transistor, means connecting the gate of the second transistor to the refresh node, the storage node being connected to the refresh node via the source-to-drain path of the second transistor, the source of clock voltage being connected to the refresh node via said capacitor, and a supply voltage connected to the refresh node via the source-to-drain path of the third transistor.
Claim 3
Dependent Claim
45 words
A device according to claim 1 wherein the capacitor includes an upper plate in the form of a polysilicon layer connected to the refresh node and a lower plate in the form of a silicon region separated from the upper plate by a thin dielectric.
Claim 4
Dependent Claim
18 words
A device according to claim 2 wherein the second transistor has a lower threshold voltage than the capacitor.
Claim 5
Dependent Claim
124 words
A memory device comprising first and second control devices each having a current path and a control electrode, a storage node, a refresh node, a voltage-dependent capacitor, a refresh clock source, the current path of the first control device connecting the storage node to the refresh node, means connecting the storage node to the control electrode of the second control device, means connecting the control electrode of the first control device to the refresh node, the refresh clock source being connected to the refresh node via said capacitor, a voltage source connected to the refresh node via the current path of the second transistor, and means for selectively coupling logic voltage to the storage node and for detecting the voltage on the storage node.
Claim 6
Dependent Claim
124 words
A memory device comprising first and second control devices each having a current path and a control electrode, a storage node, a refresh node, a voltage-dependent capacitor, a refresh clock source, the current path of the first control device connecting the storage node to the refresh node, means connecting the storage node to the control electrode of the second control device, means connecting the control electrode of the first control device to the refresh node, the refresh clock source being connected to the refresh node via said capacitor, a voltage source connected to the refresh node via the current path of the second transistor, and means for selectively coupling logic voltage to the storage node and for detecting the voltage on the storage node.
Claim 7
Dependent Claim
16 words
A device according to claim 4 wherein the control devices are insulated gate field effect transistors.
Claim 8
Dependent Claim
13 words
A device according to claim 5 wherein the capacitor is an MOS capacitor.
Claim 9
Dependent Claim
21 words
A device according to claim 6 wherein the first control device has a threshold voltage less than that of the capacitor.
Claim 10
Dependent Claim
23 words
A device according to claim 7 wherein the refresh clock is a periodic voltage of about the same magnitude as the voltage source.
References Cited (Backward Citations)
US4070653A
Cited
US4161791A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-27 | 1984-07-28 | 1985-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-27 | 1988-07-28 | 1989-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-27 | 1992-07-28 | 1993-01-27 | $7700.00 | Window Closed / Lapsed |