Digital lock detector for phase-locked loop

Claim 2

An integrated circuit including a lock detector circuit for indicating phase lock between a reference clock signal and a synthesized clock signal, the lock detector circuit for receiving from a phase detector a version of the reference clock signal, and a version of the synthesized clock signal, first and second signals such that the difference in pulse width between the first and second signals is proportional to the phase difference between the reference clock signal and the synthesized clock signal, and a third signal that resets the first and second signals when the first and second signals are simultaneously in the same state, the lock detector circuit comprising: a first delay having a duration, the first delay for receiving the first signal and providing a first delayed signal; a second delay having a duration, the second delay for receiving the second signal and providing a second delayed signal; a first shift register for receiving the second delayed signal as an input, and for receiving the version of the reference clock signal as a clock, the first shift register producing an output that indicates the state of the second delayed signal when the version of the reference clock signal transitions; a second shift register for receiving the first delayed signal as an input, and for receiving the version of the synthesized clock signal as a clock, the second shift register producing an output that indicates the state of the first delayed signal when the version of the synthesized clock signal transitions; a logic gate for receiving as inputs the first shift register output and the second shift register output, and for producing an output that is the combination of the inputs; a third shift register for receiving the logic gate output as an input, and for receiving the third signal, the third shift register providing at least one bit as an output; and a logic circuit for receiving the output from the third shift register, the logic circuit providing an output indicating phase lock when a predetermined number of bits of the third shift register output are in a predetermined state.

Claim 3

An integrated circuit as recited in claim 1, wherein the duration of the first delay is not the same as the duration of the second delay.

Claim 4

An integrated circuit as recited in claim 1, further comprising a lock-out circuit, the lock-out circuit disabling the lock detector circuit when the logic circuit output takes on the predetermined state.

Claim 5

An integrated circuit as recited in claim 1, wherein the first shift register is an edge triggerable flip-flop.

Claim 6

An integrated circuit as recited in claim 1, wherein the logic circuit is a multiple input AND gate.

Claim 7

An integrated circuit as recited in claim 1, wherein the third shift register is a multiple stage shift register.

Claim 8

An integrated circuit as recited in claim 1, wherein said first shift register output transitions from a logic low state to a logic high state to indicate the state of the second delayed signal.

Claim 9

An integrated circuit as recited in claim 1, wherein said second shift register output transitions from a logic low state to a logic high state to indicate the state of the first delayed signal.

Claim 10

An integrated circuit as recited in claim 1, wherein the first and second signals are simultaneously in a logic high state when reset.

Claim 11

An integrated circuit as recited in claim 1, wherein the third signal is for resetting the third shift register.

Claim 12

An integrated circuit as recited in claim 1, further comprising a lock-out circuit, the lock-out circuit coupled between the phase detector and the lock detector circuit for preventing the outputs of the phase detector from propagating when the logic circuit indicates lock.

Claim 13

An integrated circuit as recited in claim 1, wherein the logic circuit additionally provides an output indicating loss of phase lock when a predetermined number of bits of the third shift register output are in a state opposite the predetermined state.

Claim 14

An integrated circuit as recited in claim 12, further comprising a latch circuit, responsive to the logic circuit, for latching the phase lock and loss of phase lock outputs therefrom.

Claim 15

An integrated circuit as recited in claim 13, wherein the logic circuit includes an AND gate for providing the phase lock indication, and a NOR gate for providing the loss of phase lock indication.

Claim 16

An integrated circuit as recited in claim 14, wherein the latch circuit is a set-reset latch.

Claim 17

An integrated circuit as recited in claim 1, wherein the logic gate is an AND gate.

Claim 18

An integrated circuit including a lock detector circuit for indicating phase lock between a reference clock signal and a synthesized clock signal, the lock detector circuit comprising: a phase detector for receiving a reference clock signal and a synthesized clock signal, and for producing a version of the reference clock signal, and for producing a version of the synthesized clock signal, first and second signals such that the difference in pulse width between the first and second signals is proportional to the phase difference between the reference clock signal and the synthesized clock signal, and a third signal that resets the first and second signals when the first and second signals are simultaneously in the same state; a first delay having a duration, the first delay for receiving the first signal and providing a first delayed signal; a second delay having a duration, the second delay for receiving the second signal and providing a second delayed signal; a first shift register for receiving the second delayed signal as an input, and for receiving the version of the reference clock signal as a clock, the first shift register producing an output that indicates the state of the second delayed signal when the version of the reference clock signal transitions; a second shift register for receiving the first delayed signal as an input, and for receiving the version of the synthesized clock signal as a clock, the second shift register producing an output that indicates the state of the first delayed signal when the version of the synthesized clock signal transitions; a logic gate for receiving as inputs the first shift register output and the second shift register output, and for producing an output that is the combination of the inputs; a third shift register for receiving the logic gate output as an input, and for receiving the third signal, the third shift register providing at least one bit as an output; and a logic circuit for receiving the output from the third shift register, the logic circuit providing an output indicating phase lock when a predetermined number of bits of the third shift register output are in a predetermined state.

Claim 19

An integrated circuit including a lock detector circuit for indicating phase lock between a reference clock signal and a synthesized clock signal, the lock detector circuit comprising: a phase detector for receiving a reference clock signal and a synthesized clock signal, and for producing a version of the reference clock signal, and for producing a version of the synthesized clock signal, first and second signals such that the difference in pulse width between the first and second signals is proportional to the phase difference between the reference clock signal and the synthesized clock signal, and a third signal that resets the first and second signals when the first and second signals are simultaneously in the same state; a first delay having a duration, the first delay for receiving the first signal and providing a first delayed signal; a second delay having a duration, the second delay for receiving the second signal and providing a second delayed signal; a first shift register for receiving the second delayed signal as an input, and for receiving the version of the reference clock signal as a clock, the first shift register producing an output that indicates the state of the second delayed signal when the version of the reference clock signal transitions; a second shift register for receiving the first delayed signal as an input, and for receiving the version of the synthesized clock signal as a clock, the second shift register producing an output that indicates the state of the first delayed signal when the version of the synthesized clock signal transitions; a logic gate for receiving as inputs the first shift register output and the second shift register output, and for producing an output that is the combination of the inputs; a third shift register for receiving the logic gate output as an input, and for receiving the third signal, the third shift register providing at least one bit as an output; and a logic circuit for receiving the output from the third shift register, the logic circuit providing an output indicating phase lock when a predetermined number of bits of the third shift register output are in a predetermined state.

Claim 20

An integrated circuit as recited in claim 17, wherein the duration of the first delay is not the same as the duration of the second delay.

Claim 21

An integrated circuit as recited in claim 17, further comprising a lock-out circuit, the lock-out circuit disabling the lock detector circuit when logic circuit output takes on the predetermined state.

Claim 22

An integrated circuit as recited in claim 17, wherein the first shift register is an edge triggerable flip flop.

Claim 23

An integrated circuit as recited in claim 17, wherein the logic circuit is a multiple input AND gate.

Claim 24

An integrated circuit as recited in claim 17, wherein the third shift register is a multiple stage shift register.

Claim 25

An integrated circuit as recited in claim 17, wherein said first shift register output transitions from a logic low state to a logic high state to indicate the state of the second delayed signal.

Claim 26

An integrated circuit as recited in claim 17, wherein said second shift register output transitions from a logic low state to a logic high state to indicate the state of the first delayed signal.

Claim 27

An integrated circuit as recited in claim 23, wherein the first and second signals are simultaneously in a logic high state when reset.

Claim 28

An integrated circuit as recited in claim 23, wherein the third signal is for resetting the third shift register.

Claim 29

An integrated circuit as recited in claim 23, further comprising a lock-out circuit coupled to the lock detector circuit, the lock-out circuit for preventing outputs of the phase detector from propagating when the logic circuit indicates phase lock.

Claim 30

In an integrated circuit as recited in claim 17, wherein the logic circuit additionally provides an output indicating loss of phase lock when a predetermined number of bits of the third shift register output are in a state opposite the predetermined state.

Claim 31

In an integrated circuit as recited in claim 28, further comprising a latch circuit, responsive to the logic circuit, for latching the phase lock and loss of phase lock outputs therefrom.

Claim 32

In an integrated circuit as recited in claim 29, wherein the logic circuit includes an AND gate for providing the phase lock indication, and a NOR gate for providing the loss of phase lock indication.

Claim 33

In an integrated circuit as recited in claim 30, wherein the latch circuit is a set-reset latch.

Claim 34

An integrated circuit as recited in claim 17, wherein the logic gate is an AND gate.

Claim 35

A phase-locked loop, comprising: a controlled oscillator for receiving as an input a control signal and for producing a synthesized clock signal as an output; a loop filter for receiving a phase difference signal as an input and providing as an output the control signal input to the controlled oscillator; and a phase detector coupled for receiving a reference signal and the synthesized clock signal as inputs, the phase detector producing as an output the phase difference signal input to the loop filter; a lock detector circuit for indicating phase lock between the reference clock signal and the synthesized clock signal, the lock detector receiving from the phase detector a latched version of the reference clock signal, and a latched version of the synthesized clock signal, first and second signals such that the difference in pulse width between the first and second signals is proportional to the phase difference between the reference clock signal and the synthesized clock signal, and a third signal that resets the first and second signals when the first and second signals are simultaneously in the same state, the lock detector circuit comprising: a first delay having a duration, the first delay for receiving the first signal and providing a first delayed signal; a second delay having a duration, the second delay for receiving the second signal and providing a second delayed signal; a first shift register for receiving the second delayed signal as an input, and for receiving the latched version of the reference clock signal as a clock, the first shift register producing an output that indicates the state of the second delayed signal when the latched version of the reference clock signal transitions; a second shift register for receiving the first delayed signal as an input, and for receiving the latched version of the synthesized clock signal as a clock, the second shift register producing an output that indicates the state of the first delayed signal when the latched version of the synthesized clock signal transitions; a logic gate for receiving as inputs the first shift register output and the second shift register output, and for producing an output that is the combination of the inputs; a third shift register for receiving the logic gate output as an input, and for receiving the third signal, the third shift register providing at least one bit as an output; and a logic circuit for receiving the output from the third shift register, the logic circuit providing an output indicating phase lock when a predetermined number of bits of the third shift register output are in a predetermined state.

Claim 36

A phase-locked loop, comprising: a controlled oscillator for receiving as an input a control signal and for producing a synthesized clock signal as an output; a loop filter for receiving a phase difference signal as an input and providing as an output the control signal input to the controlled oscillator; and a phase detector coupled for receiving a reference signal and the synthesized clock signal as inputs, the phase detector producing as an output the phase difference signal input to the loop filter; a lock detector circuit for indicating phase lock between the reference clock signal and the synthesized clock signal, the lock detector receiving from the phase detector a latched version of the reference clock signal, and a latched version of the synthesized clock signal, first and second signals such that the difference in pulse width between the first and second signals is proportional to the phase difference between the reference clock signal and the synthesized clock signal, and a third signal that resets the first and second signals when the first and second signals are simultaneously in the same state, the lock detector circuit comprising: a first delay having a duration, the first delay for receiving the first signal and providing a first delayed signal; a second delay having a duration, the second delay for receiving the second signal and providing a second delayed signal; a first shift register for receiving the second delayed signal as an input, and for receiving the latched version of the reference clock signal as a clock, the first shift register producing an output that indicates the state of the second delayed signal when the latched version of the reference clock signal transitions; a second shift register for receiving the first delayed signal as an input, and for receiving the latched version of the synthesized clock signal as a clock, the second shift register producing an output that indicates the state of the first delayed signal when the latched version of the synthesized clock signal transitions; a logic gate for receiving as inputs the first shift register output and the second shift register output, and for producing an output that is the combination of the inputs; a third shift register for receiving the logic gate output as an input, and for receiving the third signal, the third shift register providing at least one bit as an output; and a logic circuit for receiving the output from the third shift register, the logic circuit providing an output indicating phase lock when a predetermined number of bits of the third shift register output are in a predetermined state.

Claim 37

A phase-lock loop as recited in claim 33, further comprising a lock-out circuit, the lock-out circuit disabling the lock detector circuit when logic circuit output takes on the predetermined state.

Claim 38

A phase-lock loop as recited in claim 33, wherein the first shift register is an edge triggerable flip-flop.

Claim 39

A phase-lock loop as recited in claim 33, wherein the logic circuit is a multiple input AND gate.

Claim 40

A phase-lock loop as recited in claim 33, wherein the third shift register is a multiple stage shift register.

Claim 41

A phase-lock loop recited in claim 33, wherein said first shift register output transitions from a logic low state to a logic high state to indicate the state of the second delayed signal.

Claim 42

A phase-lock loop as recited in claim 33, wherein said second shift register output transitions from a logic low state to a logic high state to indicate the state of the first delayed signal.

Claim 43

A phase-lock loop as recited in claim 33, wherein the first and second signals are simultaneously in a logic high state when reset.

Claim 44

A phase-lock loop as recited in claim 33, wherein the third signal is for resetting the third shift register.

Claim 45

A phase-lock loop as recited in claim 33, further comprising a lock-out circuit, the lock-out circuit for preventing outputs of the phase detector from propagating when the logic circuit indicates phase lock.

Claim 46

An integrated circuit as recited in claim 33, wherein the logic gate is an AND gate.

Claim 47

An integrated circuit including a lock detector circuit for indicating phase lock between a reference clock signal and a synthesized clock signal, the lock detector circuit, for receiving a version of the reference clock signal, and a version of the synthesized clock signal, first and second signals such that the difference in pulse width between the first and second signals is proportional to the phase difference between the reference clock signal and the synthesized clock signal, and a third signal that resets the first and second signals when the first and second signals are simultaneously in the same state, the lock detector circuit comprising: a first delay having a duration, the first delay for receiving the first signal and providing a first delayed signal; a second delay having a duration, the second delay for receiving the second signal and providing a second delayed signal; a first shift register for receiving the second delayed signal as an input, and for receiving the version of the reference clock signal as a clock, the first shift register producing an output that indicates the state of the second delayed signal when the version of the reference clock signal transitions; a second shift register for receiving the first delayed signal as an input, and for receiving the version of the synthesized clock signal as a clock, the second shift register output producing an output that indicates the state of the first delayed signal when the version of the synthesized clock signal transitions; and a logic circuit for receiving as inputs the first shift register output and the second shift register output, and for producing an output that is indicative of whether phase lock has occurred.

Claim 48

An integrated circuit including a lock detector circuit for indicating phase lock between a reference clock signal and a synthesized clock signal, the lock detector circuit, for receiving a version of the reference clock signal, and a version of the synthesized clock signal, first and second signals such that the difference in pulse width between the first and second signals is proportional to the phase difference between the reference clock signal and the synthesized clock signal, and a third signal that resets the first and second signals when the first and second signals are simultaneously in the same state, the lock detector circuit comprising: a first delay having a duration, the first delay for receiving the first signal and providing a first delayed signal; a second delay having a duration, the second delay for receiving the second signal and providing a second delayed signal; a first shift register for receiving the second delayed signal as an input, and for receiving the version of the reference clock signal as a clock, the first shift register producing an output that indicates the state of the second delayed signal when the version of the reference clock signal transitions; a second shift register for receiving the first delayed signal as an input, and for receiving the version of the synthesized clock signal as a clock, the second shift register output producing an output that indicates the state of the first delayed signal when the version of the synthesized clock signal transitions; and a logic circuit for receiving as inputs the first shift register output and the second shift register output, and for producing an output that is indicative of whether phase lock has occurred.

Claim 49

A phase-locked loop having a lock detector, the lock detector comprising: a circuit for providing an output signal indicating when a reference clock signal and a synthesized clock signal are within a predetermined phase difference; a shift register having multiple outputs and responsive to the circuit, for shifting the output signal of the circuit in response to a shift signal; a first logic circuit providing an output indicating phase lock of the reference and synthesized clock signals when a first number of the shift register outputs are of a first state; and a second logic circuit providing an output indicating a loss of lock of the reference and synthesized clock signals when a second number of the shift register outputs are of a second state.

Claim 50

A phase-locked loop having a lock detector, the lock detector comprising: a circuit for providing an output signal indicating when a reference clock signal and a synthesized clock signal are within a predetermined phase difference; a shift register having multiple outputs and responsive to the circuit, for shifting the output signal of the circuit in response to a shift signal; a first logic circuit providing an output indicating phase lock of the reference and synthesized clock signals when a first number of the shift register outputs are of a first state; and a second logic circuit providing an output indicating a loss of lock of the reference and synthesized clock signals when a second number of the shift register outputs are of a second state.

Claim 51

The phase-locked loop as recited in claim 45, wherein the outputs of the first and second logic circuits are latched.

Claim 52

The phase-locked loop as recited in claim 46, wherein the outputs of first and second logic circuits are latched by a set-reset flipfiop.

Claim 53

The phase-lock loop as recited in claim 45, wherein the first number is greater than the second number.

Claim 54

The phase-locked loop as recited in claim 48, wherein the first and second numbers are predetermined.