Frequency and phase error determination apparatus

Claim 2

A digital signal detector characterised in that it comprises means (13) for providing a reference signal at a frequency f, and phase p,; means (12) for providing an input signal representative of a signal at a frequency f2an and phase P 2 relative to the phase p, of the reference signal; means (16) for providing clock signals at a frequency; excess count means (11, 15, 17, 18, 35, 45, 46) responsive to the reference signals, the input signals and the clock signals for counting clock pulses during periods of enablement and providing output signals when the clock pulse count exceed preselected count values, the output signals being representative of frequency and phase differences between the input signal and the reference signal; and means (24, 45, 41, 26, 32, 33) responsive to the output signals of the excess count means for providing signals to increment the frequency f, of the reference frequency such that the frequency f, is locked to the frequency f 2 .

Claim 3

A digital signal detector according to claim 1, characterised in that the excess count means includes first synchronising means (35 coupled to receive the input signal (12) and the clock pulses - (16) for providing the input signal at a first output terminal and a signal complementary to the input signal at a second output terminal with each received clock pulse; and first and second up-down counter means (45, 46) having enable terminals coupled respectively to the first and second output terminals of the first synchronising means, and count direction control terminals coupled to receive the reference signal (13) for counting clock pulses coupled thereto and providing output pulses at overflow terminals when the clock pulses counts exceed preselected count values.

Claim 4

A digital signal detector according to claim 2, characterised in that the excess count means further includes gate means (11) coupled to receive the input signal (12) and a signal representative of the reference signal (13) for providing a signal having a predetermined logic level an output terminal when either, but not both, the input signal or the signal representative of the reference signal are at the predetermined logic level and a logic level comptementary to the predetermined logic level otherwise, second synchronising means (15) having an input terminal coupled to the output terminal of the gate means for providing the gate means output signal at a first output terminal, and a signal complementary to the gate means output signal at second output terminal, and third and fourth up-down counter means (17, 18) having enable terminals coupled respectively to the first and second output terminals of the second synchronising means, and count direction control terminals coupled to receive the signal representative of the reference signal for counting clock pulses coupled thereto and providing output pulses at overflow terminals when the clock pulse counts exceed preselected count values.

Claim 5

A digital signal detector according to claim 3, characterised in that the increment means includes first overflow counter means (48) having up-down control terminals coupled to the overflow terminals of the first and second up-down counters (45, 46), respectively, for providing carry and borrow pulses in accordance with clock pulse counts that exceed loaded count values; second overflow counter means (24) having up-down control terminals coupled to the overflow terminals of the third and fourth up-down counters (17, 18) respectively, for providing carry and borrow pulses in accordance with clock pulse counts that exceed loaded count values; first and second shift register means (41, 26) respectively coupled to receive the carry and borrow pulses from the first and second overflow counter means for serial storage in a plurality of register stages having individual output terminals; and frequency offset register means (32) coupled to an output terminal of a selected one of the plurality register stages for establishing corrected frequency control signals to alter the reference signal frequency in response to signals received from the selected one stage.

Claim 6

A digital signal detector according to claim 4, characterised in that the increment means further includes up-down logic means (33) having input terminals coupled to the overflow terminals of the first, second, third and fourth up-down counter means (45, 46, 17, 18) and an output terminal coupled to the frequency offset register means - (32) for establishing correction directions in establishing the frequency control signals.

Claim 7

A digital signal detector according to claim 5, characterised in that it further includes multiplexing means (44) coupled to receive signals representative of the reference signal (13) for sequentially providing enabling signals to a multiplicity of output terminals one of which is coupled to enable terminals of the third and fourth up-down counters (17, 18); and switch means (36) coupled to receive enabling signals from the multiplexing means and having an output terminal coupled to the count direction control terminals of the first and second up-down counter means (45, 46), a first input terminal coupled to receive the reference signal (13) and a second input terminal for selectively coupling the first and second input terminals to an output terminal in response to the enabling signals; and divider means (14, 37) coupled between the reference signal means and the second input terminal of the switch means for reducing the frequency f, by a predetermined factor.