Non-volatile memory device with high gate coupling ratio and manufacturing process therefor

Claim 1

A method of forming a semiconductor memory device including the steps as follows: providing a doped silicon semiconductor substrate coated with a glass, lower, dielectric layer covered in turn with an upper dielectric layer of silicon nitride, then forming over said upper dielectric layer a mask with an initial opening down through said mask to expose a future trench location on said upper dielectric layer, said opening having sidewalls, forming a blanket conformal deposit of a lining material layer covering said future trench location as well as covering said mask and said sidewalls of said opening through said mask to form a narrowed opening in said initial opening, etching through said narrowed opening to form a gate conductor molding trench down through said upper, silicon nitride dielectric layer and down through said lower, glass dielectric layer down to said substrate, stripping away said mask and said lining material, forming a silicon oxide layer at the base of said gate conductor molding trench, depositing a conformal floating gate conductor layer in a CVD process yielding polysilicon formed in silane and nitrogen gases, on the exposed surfaces in said gate conductor molding trench including said silicon oxide layer, leaving a narrowed trench in said floating gate conductor layer in the pattern of said gate conductor molding trench, forming a thin interelectrode ONO dielectric layer upon said floating gate conductor layer leaving a further narrowed trench in said interelectrode dielectric layer in the pattern of said gate conductor molding trench, depositing a polysilicon control gate conductor layer in a CVD process with silane and nitrogen gases, filling said further narrowed trench in said interelectrode dielectric layer and covering said ONO dielectric layer planarizing said conformal floating gate conductor layer, said floating gate conductor layer, said thin interelectrode dielectric layer, and said control gate conductor layer down to said dielectric layer by CMP, stripping away said dielectric layer, and forming self-aligned source/drain regions in said substrate.

Claim 2

A method of forming a semiconductor memory device including the steps as follows: providing a doped silicon semiconductor substrate coated with a glass, lower, dielectric layer covered in turn with an upper dielectric layer of silicon nitride, then forming over said upper dielectric layer a mask with an initial opening down through said mask to expose a future trench location on said upper dielectric layer, said opening having sidewalls, forming a blanket conformal deposit of a lining material layer covering said future trench location as well as covering said mask and said sidewalls of said opening through said mask to form a narrowed opening in said initial opening, etching through said narrowed opening to form a gate conductor molding trench down through said upper, silicon nitride dielectric layer and down through said lower, glass dielectric layer down to said substrate, stripping away said mask and said lining material, forming a silicon oxide layer at the base of said gate conductor molding trench, depositing a conformal floating gate conductor layer in a CVD process yielding polysilicon formed in silane and nitrogen gases, on the exposed surfaces in said gate conductor molding trench including said silicon oxide layer, leaving a narrowed trench in said floating gate conductor layer in the pattern of said gate conductor molding trench, forming a thin interelectrode ONO dielectric layer upon said floating gate conductor layer leaving a further narrowed trench in said interelectrode dielectric layer in the pattern of said gate conductor molding trench, depositing a polysilicon control gate conductor layer in a CVD process with silane and nitrogen gases, filling said further narrowed trench in said interelectrode dielectric layer and covering said ONO dielectric layer planarizing said conformal floating gate conductor layer, said floating gate conductor layer, said thin interelectrode dielectric layer, and said control gate conductor layer down to said dielectric layer by CMP, stripping away said dielectric layer, and forming self-aligned source/drain regions in said substrate.

Claim 5

A method of forming a semiconductor memory device including the steps as follows: providing a doped silicon semiconductor substrate coated with a glass, lower, dielectric layer covered in turn with an upper dielectric layer of silicon nitride, forming a mask with a surface and an opening through said mask, forming a blanket conformal deposit of a lining material layer upon covering said mask and the walls of said opening through said mask to narrow said opening, etching through said opening to form a gate conductor molding trench through said upper and lower dielectric layers down to said substrate, forming a silicon oxide layer at the base of said trench, depositing a conformal floating gate conductor layer on the exposed surfaces in said trench including said silicon oxide layer, leaving a narrowed trench in said floating gate conductor layer in the pattern of said gate conductor molding trench, forming a thin interelectrode dielectric layer upon said floating gate conductor layer leaving a further narrowed trench in said interelectrode dielectric layer in the pattern of said gate conductor molding trench, depositing a control gate conductor layer filling said further narrowed trench in said interelectrode dielectric layer and covering said interelectrode dielectric layer, planarizing said conformal floating gate conductor layer, said thin interelectrode dielectric layer, and said control gate conductor layer down to said silicon nitride dielectric layer, stripping away said lower and upper dielectric layers, and forming self-aligned source/drain regions in said substrate.

Claim 6

A method of forming a semiconductor memory device including the steps as follows: providing a doped silicon semiconductor substrate coated with a glass, lower, dielectric layer covered in turn with an upper dielectric layer of silicon nitride, forming a mask with a surface and an opening through said mask, forming a blanket conformal deposit of a lining material layer upon covering said mask and the walls of said opening through said mask to narrow said opening, etching through said opening to form a gate conductor molding trench through said upper and lower dielectric layers down to said substrate, forming a silicon oxide layer at the base of said trench, depositing a conformal floating gate conductor layer on the exposed surfaces in said trench including said silicon oxide layer, leaving a narrowed trench in said floating gate conductor layer in the pattern of said gate conductor molding trench, forming a thin interelectrode dielectric layer upon said floating gate conductor layer leaving a further narrowed trench in said interelectrode dielectric layer in the pattern of said gate conductor molding trench, depositing a control gate conductor layer filling said further narrowed trench in said interelectrode dielectric layer and covering said interelectrode dielectric layer, planarizing said conformal floating gate conductor layer, said thin interelectrode dielectric layer, and said control gate conductor layer down to said silicon nitride dielectric layer, stripping away said lower and upper dielectric layers, and forming self-aligned source/drain regions in said substrate.

Claim 16

A method of forming a semiconductor memory device including the steps as follows: providing a doped silicon semiconductor substrate coated with a BPSG glass, lower, dielectric layer from about 2,000 Å thick to about 4,000 Å thick covered in turn with an upper dielectric layer of silicon nitride from about 100 Å thick to about 500 Å thick, then forming over said upper dielectric layer a mask with an opening through said mask down to expose a future trench location on said upper dielectric layer, said opening having sidewalls, then forming a blanket conformal deposit of a lining material layer covering said future trench location as well as covering said mask and said sidewalls of said opening through said mask to form a narrowed opening, etching through said narrowed opening to form a gate conductor molding trench through said lower, dielectric layer and said upper, dielectric layer down to said substrate, stripping away said mask and said lining material, forming a silicon oxide layer at the base of said gate conductor molding trench from about 50 Å thick to about 200 Å thick, depositing a conformal floating gate conductor layer in a CVD process yielding a thickness about 1,000 Å thick to about 2,000 Å thick of polysilicon formed in silane gas and nitrogen gas, on the exposed surfaces in said gate conductor molding trench including said silicon oxide layer, leaving a narrowed trench in said floating gate conductor layer in the pattern of said gate conductor molding trench, forming a thin interelectrode ONO dielectric layer upon said floating gate conductor layer leaving a further narrowed trench in said interelectrode dielectric layer in the pattern of said gate conductor molding trench, depositing a control gate conductor layer in a CVD process yielding a thickness about 1,000 Å thick to about 3,000 Å thick of polysilicon formed in silane and nitrogen gases filling said further narrowed trench in said interelectrode dielectric layer planarizing said conformal floating gate conductor layer, said thin interelectrode dielectric layer, and said control gate conductor layer down to said upper dielectric layer by CMP, stripping away said upper and lower dielectric layers, and forming self-aligned source/drain regions in said substrate.

Claim 17

A method of forming a semiconductor memory device including the steps as follows: providing a doped silicon semiconductor substrate coated with a BPSG glass, lower, dielectric layer from about 2,000 Å thick to about 4,000 Å thick covered in turn with an upper dielectric layer of silicon nitride from about 100 Å thick to about 500 Å thick, then forming over said upper dielectric layer a mask with an opening through said mask down to expose a future trench location on said upper dielectric layer, said opening having sidewalls, then forming a blanket conformal deposit of a lining material layer covering said future trench location as well as covering said mask and said sidewalls of said opening through said mask to form a narrowed opening, etching through said narrowed opening to form a gate conductor molding trench through said lower, dielectric layer and said upper, dielectric layer down to said substrate, stripping away said mask and said lining material, forming a silicon oxide layer at the base of said gate conductor molding trench from about 50 Å thick to about 200 Å thick, depositing a conformal floating gate conductor layer in a CVD process yielding a thickness about 1,000 Å thick to about 2,000 Å thick of polysilicon formed in silane gas and nitrogen gas, on the exposed surfaces in said gate conductor molding trench including said silicon oxide layer, leaving a narrowed trench in said floating gate conductor layer in the pattern of said gate conductor molding trench, forming a thin interelectrode ONO dielectric layer upon said floating gate conductor layer leaving a further narrowed trench in said interelectrode dielectric layer in the pattern of said gate conductor molding trench, depositing a control gate conductor layer in a CVD process yielding a thickness about 1,000 Å thick to about 3,000 Å thick of polysilicon formed in silane and nitrogen gases filling said further narrowed trench in said interelectrode dielectric layer planarizing said conformal floating gate conductor layer, said thin interelectrode dielectric layer, and said control gate conductor layer down to said upper dielectric layer by CMP, stripping away said upper and lower dielectric layers, and forming self-aligned source/drain regions in said substrate.