Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors

Claim 1

A method of fabricating an array of non-volatile memory cells having enhanced capacitive coupling, comprising the steps of: forming trenches in a silicon substrate by masking and anisotropic plasma etching; thermally oxidizing the surface of said trenches; depositing a conformal first insulating layer in said trenches and elsewhere on said silicon substrate; etching back said first insulating layer to the surface of said silicon substrate and thereby forming planar field oxide regions, wherein said field oxide regions electrically isolate an array of device areas into column device areas and row device areas on said substrate surface; depositing a second insulating layer on said field oxide regions and elsewhere on said device areas on said silicon substrate; forming wells in said second insulating layer to said substrate surface extending over said row device areas and also said wells extending over adjacent said field oxide regions and lying between said column device areas; thermally oxidizing said silicon substrate surface in said wells thereby forming a gate oxide for said non-volatile memory cells; depositing a conformal first polysilicon layer on said second insulating layer and in said wells; patterning said first polysilicon layer leaving portions in said wells and over opposite sidewalls parallel to said column device areas, and removing portions of said first polysilicon layer on other sidewalls parallel to said row device areas and on said field oxide regions adjacent to said row device areas thereby forming floating gates; depositing an interlevel dielectric insulating layer on said patterned first polysilicon layer and elsewhere on said second insulating layer; depositing a conformal second polysilicon layer over said dielectric insulating layer and in said wells thereby filling said wells; chemical/mechanical polishing back said second polysilicon layer and said dielectric insulating layer and said first polysilicon layer to the surface of said second insulating layer thereby forming the control gate electrodes for field effect transistors (FETs) from said second polysilicon layer; removing selectively said second insulating layer to said substrate thereby leaving an array of said gate electrodes having said floating gate and said control gate with increased surface area with enhanced capacitive coupling; doping said device areas adjacent to said electrodes by ion implantation thereby forming lightly doped drains; depositing a conformal third insulating layer over said gate electrodes and elsewhere on said substrate; anisotropically blanket etch back said third insulating layer forming sidewall spacers on said gate electrodes; doping said device areas and forming source/drain contact areas and buried bit lines in said column device areas on said substrate thereby completing said array of said non-volatile memory cells.

Claim 2

A method of fabricating an array of non-volatile memory cells having enhanced capacitive coupling, comprising the steps of: forming trenches in a silicon substrate by masking and anisotropic plasma etching; thermally oxidizing the surface of said trenches; depositing a conformal first insulating layer in said trenches and elsewhere on said silicon substrate; etching back said first insulating layer to the surface of said silicon substrate and thereby forming planar field oxide regions, wherein said field oxide regions electrically isolate an array of device areas into column device areas and row device areas on said substrate surface; depositing a second insulating layer on said field oxide regions and elsewhere on said device areas on said silicon substrate; forming wells in said second insulating layer to said substrate surface extending over said row device areas and also said wells extending over adjacent said field oxide regions and lying between said column device areas; thermally oxidizing said silicon substrate surface in said wells thereby forming a gate oxide for said non-volatile memory cells; depositing a conformal first polysilicon layer on said second insulating layer and in said wells; patterning said first polysilicon layer leaving portions in said wells and over opposite sidewalls parallel to said column device areas, and removing portions of said first polysilicon layer on other sidewalls parallel to said row device areas and on said field oxide regions adjacent to said row device areas thereby forming floating gates; depositing an interlevel dielectric insulating layer on said patterned first polysilicon layer and elsewhere on said second insulating layer; depositing a conformal second polysilicon layer over said dielectric insulating layer and in said wells thereby filling said wells; chemical/mechanical polishing back said second polysilicon layer and said dielectric insulating layer and said first polysilicon layer to the surface of said second insulating layer thereby forming the control gate electrodes for field effect transistors (FETs) from said second polysilicon layer; removing selectively said second insulating layer to said substrate thereby leaving an array of said gate electrodes having said floating gate and said control gate with increased surface area with enhanced capacitive coupling; doping said device areas adjacent to said electrodes by ion implantation thereby forming lightly doped drains; depositing a conformal third insulating layer over said gate electrodes and elsewhere on said substrate; anisotropically blanket etch back said third insulating layer forming sidewall spacers on said gate electrodes; doping said device areas and forming source/drain contact areas and buried bit lines in said column device areas on said substrate thereby completing said array of said non-volatile memory cells.

Claim 12

A method of fabricating an electrically programmable read only memory (EPROM) having memory cells with enhanced capacitive coupling, comprising the steps of: forming trenches in a silicon substrate by masking and anisotropic plasma etching; thermally oxidizing the surface of said trenches; depositing a conformal first insulating layer in said trenches and elsewhere on said silicon substrate; etching back said first insulating layer to the surface of said silicon substrate and thereby forming planar field oxide regions, wherein said field oxide regions electrically isolate an array of column device areas and row device areas on said substrate surface; depositing a second insulating layer on said field oxide regions and elsewhere on said device areas on said silicon substrate; forming wells in said second insulating layer to said substrate surface extending over said row device areas and also said wells extending over adjacent said field oxide regions and lying between said column device areas; thermally oxidizing said silicon substrate surface in said wells thereby forming a gate oxide for said non-volatile memory cells; depositing a conformal first polysilicon layer on said second insulating layer and in said wells; patterning said first polysilicon layer leaving portions in said wells and over opposite sidewalls parallel to said column device areas, and removing portions of said first polysilicon layer on other sidewalls parallel to said row device areas and on said field oxide regions adjacent to said row device areas thereby forming floating gates; depositing an interlevel dielectric insulating layer on said patterned first polysilicon layer and elsewhere on said second insulating layer; depositing a conformal second polysilicon layer over said dielectric insulating layer and in said wells thereby filling said wells; chemical/mechanical polishing back said second polysilicon layer and said dielectric insulating layer and said first polysilicon layer to the surface of said second insulating layer thereby forming the control gate electrodes for field effect transistors (FETs) from said second polysilicon layer; removing selectively said second insulating layer to said substrate thereby leaving an array of said gate electrodes having said floating gate and said control gate with increased surface area with enhanced capacitive coupling; doping said device areas adjacent to said electrodes by ion implantation thereby forming lightly doped drains; depositing a conformal third insulating layer over said gate electrodes and elsewhere on said substrate; anisotropically blanket etch back said third insulating layer forming sidewall spacers on said gate electrodes; doping said device areas and forming source/drain contact areas and buried bit lines in said column device areas on said substrate thereby forming said array of said memory cells; and further, depositing a conformal fourth insulating layer over said array of said memory cells and elsewhere on said substrate; etching contact openings in said fourth insulating layer to said control gate electrodes over said field oxide regions; depositing and patterning a third polysilicon layer thereby forming word lines contacting said control gate electrodes, said word lines and said bit lines contacting peripheral circuits thereby completing said EPROM.

Claim 13

A method of fabricating an electrically programmable read only memory (EPROM) having memory cells with enhanced capacitive coupling, comprising the steps of: forming trenches in a silicon substrate by masking and anisotropic plasma etching; thermally oxidizing the surface of said trenches; depositing a conformal first insulating layer in said trenches and elsewhere on said silicon substrate; etching back said first insulating layer to the surface of said silicon substrate and thereby forming planar field oxide regions, wherein said field oxide regions electrically isolate an array of column device areas and row device areas on said substrate surface; depositing a second insulating layer on said field oxide regions and elsewhere on said device areas on said silicon substrate; forming wells in said second insulating layer to said substrate surface extending over said row device areas and also said wells extending over adjacent said field oxide regions and lying between said column device areas; thermally oxidizing said silicon substrate surface in said wells thereby forming a gate oxide for said non-volatile memory cells; depositing a conformal first polysilicon layer on said second insulating layer and in said wells; patterning said first polysilicon layer leaving portions in said wells and over opposite sidewalls parallel to said column device areas, and removing portions of said first polysilicon layer on other sidewalls parallel to said row device areas and on said field oxide regions adjacent to said row device areas thereby forming floating gates; depositing an interlevel dielectric insulating layer on said patterned first polysilicon layer and elsewhere on said second insulating layer; depositing a conformal second polysilicon layer over said dielectric insulating layer and in said wells thereby filling said wells; chemical/mechanical polishing back said second polysilicon layer and said dielectric insulating layer and said first polysilicon layer to the surface of said second insulating layer thereby forming the control gate electrodes for field effect transistors (FETs) from said second polysilicon layer; removing selectively said second insulating layer to said substrate thereby leaving an array of said gate electrodes having said floating gate and said control gate with increased surface area with enhanced capacitive coupling; doping said device areas adjacent to said electrodes by ion implantation thereby forming lightly doped drains; depositing a conformal third insulating layer over said gate electrodes and elsewhere on said substrate; anisotropically blanket etch back said third insulating layer forming sidewall spacers on said gate electrodes; doping said device areas and forming source/drain contact areas and buried bit lines in said column device areas on said substrate thereby forming said array of said memory cells; and further, depositing a conformal fourth insulating layer over said array of said memory cells and elsewhere on said substrate; etching contact openings in said fourth insulating layer to said control gate electrodes over said field oxide regions; depositing and patterning a third polysilicon layer thereby forming word lines contacting said control gate electrodes, said word lines and said bit lines contacting peripheral circuits thereby completing said EPROM.