US5441908A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Capacitor of a semiconductor device having increased effective area
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-12-18
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Granted: 1995-08-15
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Expires: 2012-12-18
Abstract
Abstract A semiconductor memory device includes a plurality of memory cells each having a single transistor and a single capacitor on a semiconductor substrate. The capacitor has a storage electrode with an externally communicated box-type tunnel in its center, one portion of the storage electrode being connected to the source region of the transistor. A method for manufacturing the semiconductor memory device is also provided. Thus, storage capacity is raised by increasing the effective area of the capacitor, and the planarizing effect is also excellent.
Inventors
- 👤 Tae-woo Lee
- 👤 Yang-goo Lee
- 👤 Byung-hak Lim
- 👤 Dong-gun Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:47
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
190 words
A method for manufacturing a semiconductor memory device including a plurality of memory cells, each said cell having a single transistor and a single capacitor on a semiconductor substrate, comprising the steps of: (a) forming a field oxide layer for defining an active region and an isolation region on said semiconductor substrate; (b) forming said transistor on said semiconductor substrate of said active region; (c) forming a first insulating layer for insulating said transistor; (d) etching said first insulating layer, thereby forming first and second contact holes for exposing source and drain regions of said transistor; (e) simultaneously forming a capacitor storage electrode having a tunnel which defines an interior surface therein which is open to an exterior of the storage electrode, and forming a bit line connected to said drain region via said second contact hole, said storage electrode being partially connected to said source region via said first contact hole; (f) forming a first dielectric layer portion and a second dielectric layer portion over said exterior and interior surfaces of said storage electrode, respectively; and (g) forming a plate electrode over said first and second dielectric layer portions.
Claim 2
Independent Claim
190 words
A method for manufacturing a semiconductor memory device including a plurality of memory cells, each said cell having a single transistor and a single capacitor on a semiconductor substrate, comprising the steps of: (a) forming a field oxide layer for defining an active region and an isolation region on said semiconductor substrate; (b) forming said transistor on said semiconductor substrate of said active region; (c) forming a first insulating layer for insulating said transistor; (d) etching said first insulating layer, thereby forming first and second contact holes for exposing source and drain regions of said transistor; (e) simultaneously forming a capacitor storage electrode having a tunnel which defines an interior surface therein which is open to an exterior of the storage electrode, and forming a bit line connected to said drain region via said second contact hole, said storage electrode being partially connected to said source region via said first contact hole; (f) forming a first dielectric layer portion and a second dielectric layer portion over said exterior and interior surfaces of said storage electrode, respectively; and (g) forming a plate electrode over said first and second dielectric layer portions.
Claim 3
Dependent Claim
158 words
A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said steps for simultaneously forming said storage electrode and said bit line further comprise the steps of: (a) forming a first material layer on the whole surface of the resultant structure, after forming said first and second contact holes; (b) forming a second insulating layer on said first material layer; (c) performing an etch-back operation upon the whole surface of said second insulating layer, thereby exposing a portion of said first material layer; (d) forming a second material layer on the whole surface of the resultant structure; (e) simultaneously etching said first and second material layers by applying a first mask pattern on said second material layer formed on said source region; (f) forming a storage electrode pattern of said capacitor and said bit line; and (g) removing the second insulating layer which remains after forming said storage electrode pattern and said bit line.
Claim 4
Dependent Claim
192 words
A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said steps for forming said storage electrode and bit line further comprise the steps of: (a) forming a first material layer on the whole surface of the resultant structure, after forming said first and second contact holes; (b) forming a second insulating layer on said first material layer; (c) performing an etch-back operation upon the whole surface of said second insulating layer to thereby expose a portion of said first material layer; (d) forming a second material layer on the whole surface of the resultant structure; (e) forming a first mask pattern on said second material layer on said source region for forming said storage electrode of said capacitor; (f) etching said second material layer by applying said first mask pattern; (g) removing the portions of said second insulating layer exposed after etching said second material layer; (h) forming a second mask pattern for forming said bit line on said first material layer on said drain region exposed by removing said insulating layer; and (i) etching said first material layer by applying said first and second mask patterns.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-08-14 | 1999-02-13 | 1999-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-14 | 2003-02-13 | 2003-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-14 | 2007-02-13 | 2007-08-15 | $7700.00 | Window Closed / Lapsed |