Stacked delta cell capacitor

Claim 1

A process for fabricating a DRAM array on a silicon substrate, said process comprising the steps of: creating active areas arranged in parallel rows and parallel columns; creating a gate dielectric layer on top of each active area; forming a first conductive layer superjacent surface of said array; forming a first dielectric layer superjacent said first conductive layer; masking and removing said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over a corresponding said gate dielectric layer; creating of a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; forming a second dielectric layer superjacent said array surface; creating a first aligned buried contact location at each said digit line junction in each said active area; forming a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; forming a third dielectric layer superjacent to said second conductive layer; masking and removing a portion of said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines; forming a first oxide layer superjacent said array surface; creating a second aligned buried contact location at each said storage node junction in each said active area; forming a third conductive layer superjacent said array surface, said third conductive layer forming a plurality of peaks and valleys and making contact to said storage mode junctions at said second buried contact locations; forming a second oxide layer superjacent said third conductive layer; planarizing said array surface down to said third conductive layer which exposes said peaks of said third conductive layer; forming a fourth conductive layer superjacent said array surface, said fourth conductive layer making direct contact to said peaks of said third conductive layer; patterning said third and fourth conductive layers to form a storage node plate at each said storage node junction, said storage node plate having a double, hollow, inverted-deltoid cross-section; removing said second oxide; forming a cell dielectric layer adjacent and coextensive with said storage node plate on inner and outer surfaces and adjacent said array surface; and forming a fifth conductive layer adjacent to and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.