US5459091A
Expired / Lapsed
US
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Method for fabricating a non-volatile memory device
Assignee: SK Hynix Inc
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Filing: 1993-10-12
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Granted: 1995-10-17
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Expires: 2013-10-12
Abstract
Abstract A method of fabricating a nonvolatile memory device including the steps of depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying an etchback process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which includes a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region extending from an end portion of the first region and perpendicular to the first region in the first direction, the interlayer insulating film being disposed between the floating gate and the control gate and providing a capacitance; implanting dopants of a second conductivity type into the substrate to form a drain having a shallow junction; removing the first oxide film; coating a second oxide film over the resultant structure; applying an anisotropic etching process to the oxide film so as to form spacers at both sidewalls of the EEPROM structure; and implanting dopants of a second conductivity type into the substrate so as to form a source and a drain having a deep junction. The nonvolatile memory device formed by the process has improved coupling ratio, programming speed, and degree of integration.
Inventors
- 👤 Hyun S. Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10B; H10B69/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686; H10D30/6891
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
276 words
A method for fabricating a nonvolatile memory device, comprising the steps of: depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying a selective etching process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which comprises a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region being extended from an end portion of the first region and perpendicular to the first region in the first direction, the interlayer insulating film being disposed between the floating gate and the control gate and providing a capacitance; implanting dopants of a second conductivity type into the substrate to form a drain having a shallow junction; removing the first oxide film; coating a second oxide film over the resultant structure; applying an anisotropic etching process to the oxide film so as to form spacers at both sidewalls of the EEPROM structure; and implanting dopants of a second conductivity type into the substrate so as to form a source and a drain having a deep junction.
Claim 2
Independent Claim
276 words
A method for fabricating a nonvolatile memory device, comprising the steps of: depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying a selective etching process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which comprises a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region being extended from an end portion of the first region and perpendicular to the first region in the first direction, the interlayer insulating film being disposed between the floating gate and the control gate and providing a capacitance; implanting dopants of a second conductivity type into the substrate to form a drain having a shallow junction; removing the first oxide film; coating a second oxide film over the resultant structure; applying an anisotropic etching process to the oxide film so as to form spacers at both sidewalls of the EEPROM structure; and implanting dopants of a second conductivity type into the substrate so as to form a source and a drain having a deep junction.
Claim 3
Independent Claim
276 words
A method for fabricating a nonvolatile memory device, comprising the steps of: depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying an anisotropic etching process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which comprises a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region being extended from an end portion of the first region and perpendicular to the first region in the first direction, the interlayer insulating film being disposed between the floating gate and the control gate and providing a capacitance; implanting dopants of a second conductivity type into the substrate to form a drain having a shallow junction; removing the first oxide film; coating a second oxide film over the resultant structure; applying an anisotropic etching process to the oxide film so as to form spacers at both sidewalls of the EEPROM structure; and implanting dopants of a second conductivity type into the substrate so as to form a source and a drain having a deep junction.
Claim 4
Independent Claim
276 words
A method for fabricating a nonvolatile memory device, comprising the steps of: depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying an anisotropic etching process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which comprises a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region being extended from an end portion of the first region and perpendicular to the first region in the first direction, the interlayer insulating film being disposed between the floating gate and the control gate and providing a capacitance; implanting dopants of a second conductivity type into the substrate to form a drain having a shallow junction; removing the first oxide film; coating a second oxide film over the resultant structure; applying an anisotropic etching process to the oxide film so as to form spacers at both sidewalls of the EEPROM structure; and implanting dopants of a second conductivity type into the substrate so as to form a source and a drain having a deep junction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-16 | 1999-04-17 | 1999-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-16 | 2003-04-17 | 2003-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-16 | 2007-04-17 | 2007-10-17 | $7700.00 | Window Closed / Lapsed |