US5583066A
Expired / Lapsed
US
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Method of fabricating nonvolatile semiconductor memory element having elevated source and drain regions
Assignee: SK Hynix Inc
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Filing: 1995-04-07
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Granted: 1996-12-10
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Expires: 2015-04-07
Abstract
Abstract This invention relates to a nonvolatile semiconductor memory element having elevated source and drain regions, a well-shaped floating gate surrounding a control gate, and leveled surface, and a method for fabricating the same. The nonvolatile semiconductor memory element includes a first conduction type substrate having a channel region, an elevated source and drain regions of second conduction type formed to have a step on the substrate separated by the channel region, a floating gate insulation film formed on exposed surfaces of the substrate corresponding to the channel region and the source and drain regions, as well-shaped floating gate formed on the floating gate insulation film on the channel region having a fixed depth and a fixed thickness, a control gate having a fixed thickness formed fully buried in the well of the floating gate so that the floating gate can surround the control gate, and an interlayer insulation film formed between the floating gate and the control gate so as to insulate the floating gate and the control gate.
Inventors
- 👤 Won Y. Jung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:07
CPC Classifications
H; H10; H10B; H10B41/00; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10B69/00; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
A method for fabricating a nonvolatile semiconductor memory element comprising the steps of: depositing an impurity doped polysilicon film on a first impurity type silicon substrate; removing portions of the impurity doped polysilicon film in a channel region to form elevated source and drain regions separated by the channel region; forming a floating gate insulation film on the elevated source and drain regions and exposed surfaces of the substrate corresponding to the channel region; forming a polysilicon film on the floating gate insulation film; etching away the polysilicon film formed on the source and drain regions to form a well-shaped floating gate in the channel region; forming an interlayer insulation film on exposed surfaces of the well-shaped floating gate and the floating gate insulation film; depositing a polysilicon film to fill an inside of the well of the well-shaped floating gate; and forming a control gate in the well by removing the polysilicon film on the interlayer insulation film formed over the source and drain regions.
Claim 2
Independent Claim
166 words
A method for fabricating a nonvolatile semiconductor memory element comprising the steps of: depositing an impurity doped polysilicon film on a first impurity type silicon substrate; removing portions of the impurity doped polysilicon film in a channel region to form elevated source and drain regions separated by the channel region; forming a floating gate insulation film on the elevated source and drain regions and exposed surfaces of the substrate corresponding to the channel region; forming a polysilicon film on the floating gate insulation film; etching away the polysilicon film formed on the source and drain regions to form a well-shaped floating gate in the channel region; forming an interlayer insulation film on exposed surfaces of the well-shaped floating gate and the floating gate insulation film; depositing a polysilicon film to fill an inside of the well of the well-shaped floating gate; and forming a control gate in the well by removing the polysilicon film on the interlayer insulation film formed over the source and drain regions.
Claim 3
Dependent Claim
27 words
The method as claimed in claim 1, wherein the floating gate insulation film is a tunneling oxide film having a thickness of 100 Å to 120 Å.
Claim 4
Dependent Claim
18 words
The method as claimed in claim 1, wherein the floating gate insulation film is a thermal oxidation film.
Claim 5
Dependent Claim
18 words
The method as claimed in claim 1, wherein the control gate has a shape of a polysilicon stud.
Claim 6
Dependent Claim
29 words
The method as claimed in claim 4, wherein the control gate is made level with the interlayer insulation film such that a top surface of the element is level.
Claim 7
Dependent Claim
17 words
The method as claimed in claim 1, wherein the interlayer insulation film is a thermal oxidation film.
Claim 8
Dependent Claim
18 words
The method as claimed in claim 1, wherein the interlayer insulation film is a chemical vapor deposition film.
Claim 9
Dependent Claim
27 words
The method as claimed in claim 1, wherein the step of etching away the polysilicon film is before the step of depositing the impurity doped polysilicon film.
Claim 10
Dependent Claim
33 words
The method as claimed in claim 1, wherein the step of etching away the polysilicon film includes the substep of etching the polysilicon film until the well-shaped floating gate insulation film is exposed.
Claim 11
Dependent Claim
33 words
The method as claimed in claim 1, further including the step of adjusting a threshold voltage by injecting impurity ions into the channel region using the source and drain regions as a mask.
Claim 12
Dependent Claim
25 words
The method as claimed in claim 1, further including the step of injecting depletion impurity ions using the source and drain regions as a mask.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |