Patent US5904548A successfully refreshed from Google Patents.
US5904548A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Trench scribe line for decreased chip spacing
Assignee: Texas Instruments Inc
•
Filing: 1996-11-21
•
Granted: 1999-05-18
•
Expires: 2016-11-21
Abstract
Abstract A method of scribing and separating chips on a semiconductor wafer (21) wherein the wafer (21) is patterned and a pattern of intersecting grooves is etched on a selected surface of the semiconductor wafer (21) in a pattern, preferably in a grid pattern, to define chip areas on that surface. Trenches (27) are then formed in the shape of the pattern and the selected surface is adhered to a tape (29). Light is then passed through the tape (29) and semiconductor wafer (21) from the pattern and a pattern of intersecting saw cuts or grooves (28) aligned with the light passing through the wafer (21) is formed. The saw cuts (28) extend from a surface of the wafer (21) opposing the selected surface and are aligned with the pattern of intersecting trenches (27).
Inventors
- 👤 John W. Orcutt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:19
CPC Classifications
H; H10; H10P; H10P54/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
85 words
A method of separating chips on a semiconductor wafer comprising the steps of: (a) providing a semiconductor wafer; (b) etching a pattern of intersecting trenches on a selected surface of said wafer to define chip areas on said surface; (c) forming a groove extending from a surface of said wafer opposing said selected surface aligned with said pattern of intersecting trenches; and (d) breaking the region of semiconductor material in said wafer between said groove and said pattern of intersecting trenches to form individual chips.
Claim 2
Independent Claim
85 words
A method of separating chips on a semiconductor wafer comprising the steps of: (a) providing a semiconductor wafer; (b) etching a pattern of intersecting trenches on a selected surface of said wafer to define chip areas on said surface; (c) forming a groove extending from a surface of said wafer opposing said selected surface aligned with said pattern of intersecting trenches; and (d) breaking the region of semiconductor material in said wafer between said groove and said pattern of intersecting trenches to form individual chips.
Claim 3
Dependent Claim
35 words
The method of claim 1 wherein said step of etching a pattern includes the steps of masking said selected surface to define a grid pattern and then etching said grid pattern to form said trenches.
Claim 4
Dependent Claim
39 words
The method of claim 1 wherein said step of forming a groove comprises the steps of passing detectable energy through said semiconductor wafer from said trenches and then forming said groove aligned with said energy passing through said trenches.
Claim 5
Dependent Claim
39 words
The method of claim 2 wherein said step of forming a groove comprises the steps of passing detectable energy through said semiconductor wafer from said trenches and then forming said groove aligned with said energy passing through said trenches.
Claim 6
Dependent Claim
49 words
The method of claim 3 wherein said energy is a light having a frequency transmissive through said semiconductor wafer, said step of forming a groove further comprises the step of adhering said wafer to a tape transmissive to light having said frequency prior to passing light through said wafer.
Claim 7
Dependent Claim
49 words
The method of claim 4 wherein said energy is a light having a frequency transmissive through said semiconductor wafer, said step of forming a groove further comprises the step of adhering said wafer to a tape transmissive to light having said frequency prior to passing light through said wafer.
References Cited (Backward Citations)
JPS5853830A
Cited
US4534804A
Cited
US4604161A
Cited
EP0305204A1
Cited
US5196378A
Cited
US5350704A
Cited
US4961821A
Cited
US5272114A
Cited
US5128282A
Cited
US5219796A
Cited
US5284792A
Cited
US5369060A
Cited
US5418190A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-17 | 2002-11-16 | 2003-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-17 | 2006-11-16 | 2007-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-17 | 2010-11-16 | 2011-05-18 | $7700.00 | Window Closed / Lapsed |