Non-volatile semiconductor memory devices

Claim 2

A non-volatile semiconductor memory device for storing multivalue data, comprising: a semiconductor layer; a source area and a drain area, which are defined on the semiconductor layer, with a channel area being defined between said source area and said drain area; a first gate insulating layer located on said channel area; a floating gate electrode located on said first gate insulating layer; a second gate insulating layer located on said floating gate electrode; and at least one control gate electrode located on said second gate insulating layer; wherein said floating gate electrode is configured to include at least a first portion and a second portion, said first portion is employed for accumulating carriers that migrate through said second gate insulating layer to said floating gate electrode, said first portion has a predetermined width, which is adjustable, and the multivalue data is stored in said first portion by adjusting the predetermined width of said first portion and the amount of hot carriers to be accumulated in said first portion.

Claim 3

The device according to claim 1, wherein the carriers have a relatively small energy.

Claim 4

The device according to claim 1, wherein said channel area includes a depletion layer having an adjustable predetermined width and said first portion has a width substantially equal to that of the depletion layer.

Claim 5

The device according to claim 1, wherein said floating gate electrode includes a plurality of columnar conductive mircrocrystals oriented to extend in a direction perpendicular to said first gate insulating layer, wherein adjoining microcrystals are insulated from one another.

Claim 6

The device according to claim 4, wherein a group of microcrystals included in said first portion and a group of microcrystals included in second portion are insulated from each other.

Claim 7

The device according to claim 1, wherein said first portion is employed for implanting hot carriers having a first conductivity and migrating from said at least one control gate electrode through said second gate insulating layer in a data writing operation.

Claim 8

The device according to claim 6, wherein said first portion is employed for implanting hot carriers having a second conductivity and migrating from said at least one control gate electrode through said second gate insulating layer in a data erasing operation.

Claim 9

The device according to claim 1, wherein said semiconductor layer has two end faces, the non-volatile semiconductor memory device further comprising two electrodes located partly on said end faces where said channel area is defined.

Claim 10

A non-volatile semiconductor memory device for storing multivalue data, comprising: a semiconductor layer; a source area and a drain area, which are defined on the semiconductor layer, with a channel area being defined between said source area and said drain area; a first gate insulating layer located on said channel area; a floating gate electrode located on said first gate insulating layer; a second gate insulating layer located on said floating gate electrode; a first control gate electrode located on said second gate insulating layer; a third gate insulating layer located on said first control gate electrode; and a second control gate electrode located on said third gate insulating layer; wherein said floating gate electrode is configured to include at least a first portion and a second portion, said first and second control gate electrodes are employed for generating hot carriers that migrate through said second gate insulating layer to said floating gate electrode, said hot carriers having a relatively small energy and being generated by applying a predetermined voltage to said first and second control gate electrodes, said first portion is employed for accumulating said to carriers, said first portion has a predetermined width, which is adjustable, and the multivalue data is stored in said first portion by adjusting the predetermined width of said first portion and the amount of hot carriers to be accumulated in said first portion.

Claim 11

A non-volatile semiconductor memory device for storing multivalue data, comprising: a semiconductor layer; a source area and a drain area, which are defined on the semiconductor layer, with a channel area being defined between said source area and said drain area; a first gate insulating layer located on said channel area; a floating gate electrode located on said first gate insulating layer; a second gate insulating layer located on said floating gate electrode; a first control gate electrode located on said second gate insulating layer; a third gate insulating layer located on said first control gate electrode; and a second control gate electrode located on said third gate insulating layer; wherein said floating gate electrode is configured to include at least a first portion and a second portion, said first and second control gate electrodes are employed for generating hot carriers that migrate through said second gate insulating layer to said floating gate electrode, said hot carriers having a relatively small energy and being generated by applying a predetermined voltage to said first and second control gate electrodes, said first portion is employed for accumulating said to carriers, said first portion has a predetermined width, which is adjustable, and the multivalue data is stored in said first portion by adjusting the predetermined width of said first portion and the amount of hot carriers to be accumulated in said first portion.

Claim 12

The device according to claim 9, wherein said channel area includes a depletion layer having an adjustable predetermined width and said first portion has a width substantially equal to that of the depletion layer.

Claim 13

The device according to claim 9, wherein said floating gate electrode includes a plurality of columnar conductive microcrystals oriented to extend in a direction perpendicular to said first gate insulating layer, wherein adjoining microcrystals are insulated from one another.

Claim 14

The device according to claim 11, wherein a first group of said microcrystals is included in said first portion and a second group of said microcrystals is included in said second portion.

Claim 15

The device according to claim 9, wherein said first portion is employed for implanting hot carriers having a first conductivity and migrating from said first control gate electrode through said second gate insulating layer in a data writing operation.

Claim 16

The device according to claim 13, wherein said first portion is employed for implanting hot carriers having a second conductivity and migrating from said first control gate electrode through said second gate insulating layer in a data erasing operation.

Claim 17

The device according to claim 9, wherein said semiconductor layer has two end faces, the non-volatile semiconductor memory device further comprising two electrodes located partly on said end faces where said channel area is defined.

Claim 18

A non-volatile semiconductor memory device, comprising: a semiconductor layer; a source area and a drain area, which are defined on the semiconductor layer, with a channel area being defined between said source area and said drain area; a first gate insulating layer located on said channel area; a floating gate electrode located on said first gate insulating layer; a second gate insulating layer located on said floating gate electrode; a semiconductor gate electrode located on said second gate insulating layer; and a metallic gate electrode located on said semiconductor gate electrode; wherein said floating gate electrode is configured to include at least a first portion and a second portion, said semiconductor and metallic gate electrodes are employed for generating hot carriers that migrate through said second gate insulating layer to said floating gate electrode, said hot carriers having a relatively small energy and being generated by applying a predetermined voltage to said semiconductor and metallic gate electrodes, and said first portion is employed for accumulating said hot carriers, and wherein the amount of hot carriers to be accumulated in said first portion is adjusted depending on a data value.

Claim 19

A non-volatile semiconductor memory device, comprising: a semiconductor layer; a source area and a drain area, which are defined on the semiconductor layer, with a channel area being defined between said source area and said drain area; a first gate insulating layer located on said channel area; a floating gate electrode located on said first gate insulating layer; a second gate insulating layer located on said floating gate electrode; a semiconductor gate electrode located on said second gate insulating layer; and a metallic gate electrode located on said semiconductor gate electrode; wherein said floating gate electrode is configured to include at least a first portion and a second portion, said semiconductor and metallic gate electrodes are employed for generating hot carriers that migrate through said second gate insulating layer to said floating gate electrode, said hot carriers having a relatively small energy and being generated by applying a predetermined voltage to said semiconductor and metallic gate electrodes, and said first portion is employed for accumulating said hot carriers, and wherein the amount of hot carriers to be accumulated in said first portion is adjusted depending on a data value.

Claim 20

The device according to claim 16, wherein said first portion has a predetermined width, which is adjustable.

Claim 21

The device according to claim 17, wherein said data is multivalue data.

Claim 22

The device according to claim 16, wherein said channel area includes a depletion layer having an adjustable predetermined width and said first portion has a width substantially equal to that of the depletion layer.

Claim 23

The device according to claim 16, wherein said floating gate electrode includes a plurality of columnar conductive microcrystals oriented to extend in a direction perpendicular to said first gate insulating layer, wherein adjoining microcrystals are insulated from one another.

Claim 24

The device according to claim 20, wherein a first group of said microcrystals is included in said first portion and a second group of said microcrystals is included in said second portion.

Claim 25

The device according to claim 16, wherein said first portion is employed for implanting hot carriers having a first conductivity and migrating from said semiconductor gate electrode through said second gate insulating layer in a data writing operation.

Claim 26

The device according to claim 22, wherein said first portion is employed for implanting hot carriers having a second conductivity and migrating from said semiconductor gate electrode through said second gate insulating layer in a data erasing operation.

Claim 27

The device according to claim 16, where said semiconductor and metallic gate electrodes comprise a Schottky junction.

Claim 28

The device according to claim 24, said semiconductor gate electrode is made of polysilicon.

Claim 29

A non-volatile semiconductor memory device, comprising: a semiconductor layer having a first conductivity; two first semiconductor areas defined on the semiconductor layer and having a second conductivity; a pillar formed over the channel area and extending perpendicular from said semiconductor layer, said pillar including two side walls and a second semiconductor area defined at an upper portion of said pillar, said second semiconductor area having the second conductivity; two first gate insulating layers respectively located on the two walls of said pillar; two floating gate electrodes respectively located on said two first gate insulating layers, each of said floating gate electrodes configured to be divided into a first portion and a second portion; two second gate insulating layers respectively located on said two floating gate electrodes; two first control gate electrodes respectively located on said two second gate insulating layers; two third gate insulating layers respectively located on said two first control gate electrodes; and two second control gate electrodes respectively located on said two third gate insulating layers; wherein said first and second control gate electrodes on one side wall of said pillar and said first and second control gate electrodes on the other side wall of said pillar are employed for generating hot carriers that respectively migrate from said first control gate electrode through the second gate insulating layer to said floating gate electrode, said hot carriers having a relatively small energy and being generated by applying a predetermined voltage to said respective first and second control gate electrodes, wherein said first portion of each of said floating gate electrodes is employed for accumulating said hot carriers, and wherein the amount of hot carriers to be accumulated in said first portion is adjusted depending on a data value.

Claim 30

A non-volatile semiconductor memory device, comprising: a semiconductor layer having a first conductivity; two first semiconductor areas defined on the semiconductor layer and having a second conductivity; a pillar formed over the channel area and extending perpendicular from said semiconductor layer, said pillar including two side walls and a second semiconductor area defined at an upper portion of said pillar, said second semiconductor area having the second conductivity; two first gate insulating layers respectively located on the two walls of said pillar; two floating gate electrodes respectively located on said two first gate insulating layers, each of said floating gate electrodes configured to be divided into a first portion and a second portion; two second gate insulating layers respectively located on said two floating gate electrodes; two first control gate electrodes respectively located on said two second gate insulating layers; two third gate insulating layers respectively located on said two first control gate electrodes; and two second control gate electrodes respectively located on said two third gate insulating layers; wherein said first and second control gate electrodes on one side wall of said pillar and said first and second control gate electrodes on the other side wall of said pillar are employed for generating hot carriers that respectively migrate from said first control gate electrode through the second gate insulating layer to said floating gate electrode, said hot carriers having a relatively small energy and being generated by applying a predetermined voltage to said respective first and second control gate electrodes, wherein said first portion of each of said floating gate electrodes is employed for accumulating said hot carriers, and wherein the amount of hot carriers to be accumulated in said first portion is adjusted depending on a data value.

Claim 31

The device according to claim 26, wherein said first portion of said floating gate electrodes has a predetermined width, which is adjustable.

Claim 32

The device according to claim 27, wherein said data is multivalue data.

Claim 33

The device according to claim 26, wherein said channel area includes a depletion layer having an adjustable predetermined width, and wherein said first portion of said floating gate electrodes has a width substantially equal to that of the depletion layer in said channel area.

Claim 34

The device according to claim 26, wherein each of said floating gate electrodes includes a plurality of columnar conductive microcrystals oriented to extend in a direction perpendicular to an associated one of said first gate insulating layers, wherein adjoining microcrystals are insulated from one another.

Claim 35

The device according to claim 30, wherein a first group of said microcrystals is included in said first portion of each of said floating gate electrodes and a second group of said microcrystals is included in said second portion of each of said floating gate electrodes.

Claim 36

The device according to claim 26, wherein said first portion of each of said floating gate electrodes is employed for implanting hot carriers that migrate from said first control gate electrodes through said second gate insulating layers in a data writing operation.

Claim 37

The device according to claim 26, wherein said first portion of each of said floating gate electrodes is employed for implanting hot carriers that migrate from said first control gate electrodes through said second gate insulating layers in a data erasing operation.

Claim 38

The device according to claim 26, wherein said pillar has two end faces, the non-volatile semiconductor memory device further comprising two electrodes located partly on said end faces where said channel area is defined.