Latch structure for ripple domino logic

Claim 2

A domino circuit comprising: (a) a logic function circuit segment, said logic function circuit segment being selectively operable to provide a logic output signal in response to a selected input signal; (b) a domino output latch segment connected to said logic function circuit segment, the domino output latch segment being arranged to receive said logic output signal and provide a data output signal from said domino circuit, said domino output latch segment being operable to apply both inverting and latching functions to said logic output signal in providing said data output signal from said domino circuit; and (c) holding circuitry coupled to said logic function circuit segment and said domino output latch segment, said holding circuitry being selectively operable to impose a hold state within said domino circuit whereby a value of the data output signal is maintained over a period of time in accordance with an independently generated HOLD signal.

Claim 3

The domino circuit as set forth in claim 1 wherein said logic function circuit segment comprises a MUX circuit.

Claim 4

The domino circuit as set forth in claim 1 further comprising: (a) scanning circuitry coupled to said output latch segment, said scanning circuitry being selectively operable for scan testing said domino circuit.

Claim 5

The domino circuit as set forth in claim 1, wherein the domino output latch segment comprises: (a) a first transistor connected between a first logic voltage level bus and an output node; (b) a second transistor connected between said output node and a first common point, said first and second transistors being arranged for receiving said logic output signal from the logic function circuit segment; (c) a third transistor connected between said first common point and a second logic voltage level bus, and being arranged for receiving a timing clock signal; (d) a fourth transistor connected between said first common point and said second logic voltage level bus; (e) a fifth transistor and a sixth transistor, said fifth transistor being arranged for connection between the first logic voltage level bus and said sixth transistor, said sixth transistor being connected to said output node, said fifth transistor having an input terminal connected to an input terminal of said third transistor for receiving said clock signal, said sixth transistor having an input terminal connected to an input terminal of said fourth transistor; and (f) a seventh transistor and an eighth transistor, said seventh and eighth transistors being serially connected between the first logic voltage level bus and the second logic voltage level bus, said input terminal of said sixth transistor being connected to a common point connecting said seventh and eighth transistors, said seventh and eighth transistors having input terminals thereof connected together to the output node.

Claim 6

A domino circuit comprising: (a) a logic function circuit segment, said logic function circuit segment being selectively operable to provide a logic output signal in response to an input signal; (b) a domino output latch segment connected to said logic function circuit segment within said domino circuit, said domino output latch segment being arranged to receive said logic output signal and provide a data output signal from said domino circuit, said domino output latch segment being operable to apply both inverting and latching functions to said logic output signal in providing said data output signal from said domino circuit; and (c) scanning circuitry coupled to the domino output latch segment, said scanning circuitry for providing a scan output in response to a scan input signal and a first and second pair of complementary clock signals.

Claim 7

A domino circuit comprising: (a) a logic function circuit segment, said logic function circuit segment being selectively operable to provide a logic output signal in response to an input signal; (b) a domino output latch segment connected to said logic function circuit segment within said domino circuit, said domino output latch segment being arranged to receive said logic output signal and provide a data output signal from said domino circuit, said domino output latch segment being operable to apply both inverting and latching functions to said logic output signal in providing said data output signal from said domino circuit; and (c) scanning circuitry coupled to the domino output latch segment, said scanning circuitry for providing a scan output in response to a scan input signal and a first and second pair of complementary clock signals.

Claim 8

The domino circuit as set forth in claim 5 wherein the scanning circuitry is coupled to the domino latch circuit segment at points removed from an output node on which the data output signal is applied.

Claim 9

The domino circuit as set forth in claim 5, wherein the domino output latch segment comprises: (a) a first transistor connected between a first logic voltage level bus and an output node; (b) a second transistor connected between said output node and a first common point, said first and second transistors being arranged for receiving said logic output signal from the logic function circuit segment; (c) a third transistor connected between said first common point and a second logic voltage level bus, and being arranged for receiving a timing clock signal; (d) a fourth transistor connected between said first common point and said second logic voltage level bus; (e) a fifth transistor and a sixth transistor, said fifth transistor being arranged for connection between the first logic voltage level bus and said sixth transistor, said sixth transistor being connected to said output node, said fifth transistor having an input terminal connected to an input terminal of said third transistor for receiving said clock signal, said sixth transistor having an input terminal connected to an input terminal of said fourth transistor; and (f) a seventh transistor and an eighth transistor, said seventh and eighth transistors being serially connected between the first logic voltage level bus and the second logic voltage level bus, said input terminal of said sixth transistor being connected to a common point connecting said seventh and eighth transistors, said seventh and eighth transistors having input terminals thereof connected together to the output node.