US5646557A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system and method for improving performance of domino-type logic using multiphase clocks
Assignee: International Business Machines Corp
•
Filing: 1995-07-31
•
Granted: 1997-07-08
•
Expires: 2015-07-31
Abstract
Abstract A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit for a predetermined portion of a clock cycle. The output circuit may also include a pair of control transistors to allow the output latching circuit to be turned off during the evaluate portion of the clock cycle thus improving the speed of the domino logic circuit. During the first half of the reset portion of each cycle, the output latching circuit is active and allows the circuit to retain its output state. During the time the passgates are turned off, the evaluate circuit is disconnected and may begin resetting. During the second half of the reset portion of the clocking signal, the passgates open, which allows the output stage to be reset. Since the two additional transistors in the output circuit are controlled by the same signals which control the passgates, the circuit is relatively cheap since only the two transistors must be added to the circuit.
Inventors
- 👤 Stephen Larry Runyon
- 👤 Eric Bernard Schorn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
A logic circuit for use in a data processing system, comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; a feedback latch output circuit having a clock signal input for holding said output of said evaluation circuit for a predetermined portion of a clock cycle; and wherein said evaluation circuit comprises: a p type precharge transistor having a first terminal thereof connected to a voltage source and a second terminal connected to said output and a terminal of an n type evaluation transistor, and having a third terminal receiving a clock signal; and one or more n type evaluation transistors connected between said p type precharge transistor and a common return, each of said n type evaluation transistors having an input receiving a logic signal to be evaluated.
Claim 2
Dependent Claim
148 words
A logic circuit for use in a data processing system, comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; a feedback latch output circuit having a clock signal input for holding said output of said evaluation circuit for a predetermined portion of a clock cycle; and wherein said evaluation circuit comprises: a p type precharge transistor having a first terminal thereof connected to a voltage source and a second terminal connected to said output and a terminal of an n type evaluation transistor, and having a third terminal receiving a clock signal; and one or more n type evaluation transistors connected between said p type precharge transistor and a common return, each of said n type evaluation transistors having an input receiving a logic signal to be evaluated.
Claim 3
Dependent Claim
93 words
A logic circuit for use in a data processing system comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; a feedback latch output circuit having a clock signal input for holding said output of said evaluation circuit for a predetermined portion of a clock cycle; and wherein said passgate circuit comprises: a complementary pair of transistors connected between said output of said evaluation circuit and an input to said feedback latch output circuit.
Claim 4
Dependent Claim
93 words
A logic circuit for use in a data processing system comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; a feedback latch output circuit having a clock signal input for holding said output of said evaluation circuit for a predetermined portion of a clock cycle; and wherein said passgate circuit comprises: a complementary pair of transistors connected between said output of said evaluation circuit and an input to said feedback latch output circuit.
Claim 5
Dependent Claim
249 words
A logic circuit for use in a data processing system, comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; a feedback latch output circuit for holding said output of said evaluation circuit for a predetermined portion of a clock cycle; and wherein said feedback latch output circuit comprises: an inverter circuit having an input connected to an output of said passgate circuit and an output, said output connected to control terminals of first and second feedback transistors; said first feedback transistor being a p type transistor having one terminal thereof connected to a voltage source and a second terminal thereof connected to said input of said inverter circuit; and said second feedback transistor being an n type transistor having one terminal thereof connected to a common return and a second terminal thereof connected to said input of said inverter circuit; and wherein said feedback latch output circuit further comprises: a third feedback transistor being a p type transistor having one terminal thereof connected between said voltage source and said one terminal of said first feedback transistor, and a control terminal thereof connected to a first clock cycle control signal; and a fourth transistor being an n type transistor having one terminal thereof connected between said one terminal of said second feedback transistor and said common return, and a control terminal thereof connected to a second clock cycle control signal.
Claim 6
Dependent Claim
249 words
A logic circuit for use in a data processing system, comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; a feedback latch output circuit for holding said output of said evaluation circuit for a predetermined portion of a clock cycle; and wherein said feedback latch output circuit comprises: an inverter circuit having an input connected to an output of said passgate circuit and an output, said output connected to control terminals of first and second feedback transistors; said first feedback transistor being a p type transistor having one terminal thereof connected to a voltage source and a second terminal thereof connected to said input of said inverter circuit; and said second feedback transistor being an n type transistor having one terminal thereof connected to a common return and a second terminal thereof connected to said input of said inverter circuit; and wherein said feedback latch output circuit further comprises: a third feedback transistor being a p type transistor having one terminal thereof connected between said voltage source and said one terminal of said first feedback transistor, and a control terminal thereof connected to a first clock cycle control signal; and a fourth transistor being an n type transistor having one terminal thereof connected between said one terminal of said second feedback transistor and said common return, and a control terminal thereof connected to a second clock cycle control signal.
Claim 7
Dependent Claim
66 words
A logic circuit for use in a data processing system, comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; and a feedback latch output circuit having a clock signal input for holding said output of said evaluation circuit for a predetermined portion of a clock cycle.
Claim 8
Dependent Claim
66 words
A logic circuit for use in a data processing system, comprising: an evaluation circuit for evaluating logic inputs to said logic circuit; a passgate circuit for controlling transmission of an output from said evaluation circuit to an output circuit; and a feedback latch output circuit having a clock signal input for holding said output of said evaluation circuit for a predetermined portion of a clock cycle.
References Cited (Backward Citations)
US3646369A
Cited
US4700086A
Cited
US4899066A
Cited
US4780626A
Cited
US4849658A
Cited
US5065048A
Cited
US5070262A
Cited
US5041742A
Cited
US5041742B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |