Scan test circuit and semiconductor integrated circuit device with scan test circuit

Claim 1

In a scan test circuit having a first input terminal for inputting first data of one bit, a second input terminal for inputting second data as serial data including predetermined scan test data, a third input terminal for inputting an operation switching signal for determining a scan operation and a normal operation, an input selector means for selecting one of said first data and said second data in response to the supply of said operation switching signal and outputting selected data, a register means for holding said selected data as hold data, a first output terminal for outputting first output data corresponding to said first data, and a second output terminal for outputting second output data corresponding to said second data, said scan test circuit being operable to carry out scanning operation such that, during normal operation, a plurality of under-test circuits are caused to be operated independently with one another and, during test operation, said plurality of under-test circuits are connected in series and said second data are supplied to a first-stage under-test circuit of said plurality of under-test circuits, and test results corresponding to said second data are outputted from a last-stage under-test circuit of said plurality of under-test circuits, the improvement comprising: a latch means which latches said operation switching signal and generates an operation switching latch signal; and a selector control means which is provided in said input selector means and which selects one of said first data and said second data in response to the supply of said operation switching signal and said operation switching latch signal and outputs the selected data.