Semiconductor memory device operable with reduced current consumption immediately after power-on

Claim 2

A semiconductor memory device having a plurality of memory cells comprising: a self-refresh control circuit including a timer, for generating a control signal for refreshing storage data of said plurality of memory cells at predetermined time intervals in accordance with an output signal of said timer when activated, said timer including a timer circuit for driving the output signal into an active state when an activated state of said self-refresh control circuit is maintained for a prescribed period of time; and an initializing circuit for activating said self-refresh control circuit in response to a start of external supply of a power supply voltage to said semiconductor memory device.

Claim 3

The semiconductor memory device according to claim 1, wherein said initializing circuit includes; a dummy cycle detecting circuit for detecting a designation of a dummy cycle for initializing an internal circuit of said semiconductor memory device in accordance with an externally supplied operation cycle designation signal, and a circuit for deactivating said self-refresh control circuit in response to an activation of a dummy cycle detection signal generated from said dummy cycle detecting circuit.

Claim 4

The semiconductor memory device according to claim 1, wherein said initializing circuit includes: a power on detecting circuit coupled to an external power supply node receiving the externally supplied power supply voltage, for detecting a supply of the power supply voltage to said semiconductor memory device in accordance with the power supply voltage on said external power supply node, and for activating said self-refresh control circuit upon detection of a start of the supply of the power supply voltage.

Claim 5

The semiconductor memory device according to claim 1, wherein said initializing circuit includes; a power on detecting circuit coupled to an external power supply node receiving an externally supplied power supply voltage, detecting a start of supply of the power supply voltage to said semiconductor memory device in accordance with the power supply voltage on said external power supply node, and activating a power on detection signal upon detection of said start of the supply of the power supply voltage, and a delay circuit for delaying and applying the power on detection signal generated from said power on detecting circuit to said self-refresh control circuit, to activate said self-refresh control circuit.

Claim 6

The semiconductor memory device according to claim 1, wherein said initializing circuit includes; a circuit enabled in response to an activation of an externally supplied operation cycle defining signal, for activating said self-refresh control circuit in response to the start of the supply of the power supply voltage.

Claim 7

A semiconductor memory device having a plurality of memory cells, comprising: a self-refresh control circuit including a timer, for generating a control signal for refreshing storage data of said plurality of memory cells at predetermined time intervals in accordance with an output signal of said timer when activated; and an initializing circuit for activating said self-refresh control circuit in response to a start of external supply of a power supply voltage to said semiconductor memory device, wherein said initializing circuit includes: a first gate circuit being enabled to pass an externally supplied first operation cycle defining signal in response to the start of the supply of the power supply voltage, dummy cycle detecting means responsive to said first operation cycle defining signal for detecting a designation of a dummy cycle for setting an internal circuit in said semiconductor memory device to an initial state, and for activating a dummy cycle detection signal upon detection of the designation of the dummy cycle, a second gate circuit for holding a second operation cycle defining signal in an inactive state in response to the inactive state of the dummy cycle detection signal from said dummy cycle detecting means, and passing said second operation cycle defining signal in response to the active state of said dummy cycle detection signal, and a timing detecting circuit receiving output signals of said first and second gate circuits, for activating said self-refresh control circuit when the received output signals satisfy a predetermined timing condition.

Claim 8

A semiconductor memory device having a plurality of memory cells, comprising: a self-refresh control circuit including a timer, for generating a control signal for refreshing storage data of said plurality of memory cells at predetermined time intervals in accordance with an output signal of said timer when activated; and an initializing circuit for activating said self-refresh control circuit in response to a start of external supply of a power supply voltage to said semiconductor memory device, wherein said initializing circuit includes: a first gate circuit being enabled to pass an externally supplied first operation cycle defining signal in response to the start of the supply of the power supply voltage, dummy cycle detecting means responsive to said first operation cycle defining signal for detecting a designation of a dummy cycle for setting an internal circuit in said semiconductor memory device to an initial state, and for activating a dummy cycle detection signal upon detection of the designation of the dummy cycle, a second gate circuit for holding a second operation cycle defining signal in an inactive state in response to the inactive state of the dummy cycle detection signal from said dummy cycle detecting means, and passing said second operation cycle defining signal in response to the active state of said dummy cycle detection signal, and a timing detecting circuit receiving output signals of said first and second gate circuits, for activating said self-refresh control circuit when the received output signals satisfy a predetermined timing condition.

Claim 9

The semiconductor memory device according to claim 1, further comprising: an internal voltage-down converting circuit for lowering said externally supplied power supply voltage to generate an internal power supply voltage when activated, wherein said plurality of memory cells are arranged in a matrix form, said self-refresh control circuit includes means for generating a row select instructing signal for driving a row of said plurality of memory cells to a selected state when activated, and said internal voltage down converting circuit is activated when said row select instructing signal is active.

Claim 10

The semiconductor memory device according to claim 1, wherein said timer circuit is responsive to said initializing circuit for measuring the prescribed time to generate said control signal when the prescribed time elapses.

Claim 11

The semiconductor memory device according to claim 6, wherein said self-refresh control circuit includes means responsive to said timing detecting circuit outputting an activating signal for first generating said control signal and then generating said control signal in accordance with an output signal of said timer.

Claim 12

The semiconductor memory device according to claim 1, wherein said initializing circuit includes, a dummy cycle detecting circuit responsive to an operation cycle defining signal for detecting whether a dummy cycle mode of operation is designated, said operation cycle defining signal defining an operation cycle of said semiconductor memory device, and said dummy cycle being performed for initializing said semiconductor memory device, and a gate for activating said refresh control circuit in response to said operation cycle defining signal being active and to said dummy cycle detecting circuit outputting an inactive signal indicating that no dummy cycle is designated.