Semiconductor memory device with a self-initializing circuit operable after supply of power

Claim 2

A semiconductor memory device comprising: an internal circuit to be initialized upon start of supply of a supply voltage; initialization control means for initializing and control said internal circuit in response to an applied clock pulse; a timer circuit detecting elapse of a redetermined time length after the start of supply of the supply voltage and supplying a switching control signal; internal clock pulse generating means for receiving the supply voltage and generating the internal clock pulse; and a transfer gate circuit receiving an externally applied state control clock pulse and the internal clock pulse, and responsive to said switching control signal from said timer circuit for selectively applying one of said externally applied state control clock pulse and said internal clock pulse to said initialization control means.

Claim 3

A semiconductor memory device according to claim 1, wherein said transfer gate circuit is responsive to said switching control signal from said timer circuit to selectively apply the internal clock pulse to said initialization control means during said predetermined time length after the start of supply of the supply voltage and to selectively apply the externally applied state control clock pulse to said initialization control means after the elapse of said predetermined time length.

Claim 4

A semiconductor memory device according to claim 1, wherein said transfer gate circuit includes an output node, first switching means connected to said output node for receiving the externally applied state control clock pulse, and second switching means connected to said output node for receiving the internal clock pulse, said first and second switching means being selectively turned on in response to said time elapse detecting means.

Claim 5

A semiconductor memory device according to claim 1, wherein said timer circuit is operated under the supply of the supply voltage, and said transfer gate circuit selectively applies one of said externally applied state control clock pulse and said internal clock pulse to said initialization control means in response to said switching control signal supplied from said timer circuit.

Claim 6

A semiconductor memory device according to claim 1, wherein said internal clock pulse generating means includes ring oscillator circuit means for receiving the supply voltage and generating said internal clock pulse.

Claim 7

A semiconductor memory device according to claim 1, wherein said internal circuit includes counter circuit means for generating a count signal for controlling said memory device, and said initialization control means includes reset circuit means responsive to an applied clock pulse for resetting said counter circuit means.

Claim 8

A semiconductor memory device according to claim 4, wherein said timer circuit includes RC integrating circuit means for receiving the supply voltage and having a time constant which depends on said predetermined time length, and voltage comparing means for comparing an output voltage level of said RC integrating circuit means with a predetermined threshold voltage.

Claim 9

A semiconductor memory device according to claim 1, wherein said internal clock pulse generating means includes dummy clock pulse generating means for generating a dummy clock pulse for operating said memory device under a dummy cycle.

Claim 10

A semiconductor memory device according to claim 1, wherein said externally applied state control clock pulse is an externally applied row address strobe signal.

Claim 11

A semiconductor memory device according to claim 6, further comprising a memory cell array including a plurality of memory cells disposed in rows and columns, wherein said counter circuit means includes a refresh counter which generates a refresh count signal for refreshing a data signal stored in said memory cell array, and said reset circuit means is responsive to an applied clock pulse to reset said refresh counter.

Claim 12

A semiconductor memory device according to claim 1, wherein said memory device is a dynamic random access memory.

Claim 13

A dynamic random access memory device comprising: a memory cell array including a plurality of memory cells disposed in rows and columns; a refresh counter for generating a refresh count signal for refreshing a data signal stored in said memory cell array; a reset circuit for resetting said refresh counter in response to an applied clock pulse; a timer circuit supplied with a supply voltage for detecting elapse of a predetermined time length after supply of the supply voltage and supplying a switching control signal; a ring oscillator supplied with the supply voltage for generating a dummy clock pulse for operating said memory device under a dummy cycle; and a transfer gate circuit receiving the dummy clock pulse and an externally applied row address strobe signal, and response to said switching control signal supplied from said timer circuit for selectively supplying one of said dummy clock pulse and said row address strobe signal to said reset circuit, said transfer gate applying the dummy clock pulse to said reset circuit during said predetermined time length after the start of supply of the supply voltage and applying the row address strobe signal to said reset circuit after the elapse of said predetermined time length.

Claim 14

A dynamic random access memory device comprising: a memory cell array including a plurality of memory cells disposed in rows and columns; a refresh counter for generating a refresh count signal for refreshing a data signal stored in said memory cell array; a reset circuit for resetting said refresh counter in response to an applied clock pulse; a timer circuit supplied with a supply voltage for detecting elapse of a predetermined time length after supply of the supply voltage and supplying a switching control signal; a ring oscillator supplied with the supply voltage for generating a dummy clock pulse for operating said memory device under a dummy cycle; and a transfer gate circuit receiving the dummy clock pulse and an externally applied row address strobe signal, and response to said switching control signal supplied from said timer circuit for selectively supplying one of said dummy clock pulse and said row address strobe signal to said reset circuit, said transfer gate applying the dummy clock pulse to said reset circuit during said predetermined time length after the start of supply of the supply voltage and applying the row address strobe signal to said reset circuit after the elapse of said predetermined time length.