US5594699A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DRAM with reduced electric power consumption
Assignee: Fujitsu VLSI Ltd
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Filing: 1994-09-16
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Granted: 1997-01-14
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Expires: 2014-09-16
Abstract
Abstract A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.
Inventors
- 👤 Yukihiro Nomura
- 👤 Yasuharu Satoh
- 👤 Yoshihiro Takemae
- 👤 Takaaki Furuyama
- 👤 Mitsuhiro Nagao
- 👤 Masahiro Niimi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:47
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/4063; G11C11/407; G11C11/4074; G11C5/143
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
88 words
A DRAM (Dynamic Random Access Memory) having a plurality of memory cells comprising: a data read/write circuit reading or writing data for the memory cells; a self-refresh circuit refreshing data stored in the memory cells; and power supply means for supplying power supply voltage to said data read/write circuit and said self-refresh circuit, said power supply voltage having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein said second voltage level is smaller than said first voltage level.
Claim 2
Dependent Claim
88 words
A DRAM (Dynamic Random Access Memory) having a plurality of memory cells comprising: a data read/write circuit reading or writing data for the memory cells; a self-refresh circuit refreshing data stored in the memory cells; and power supply means for supplying power supply voltage to said data read/write circuit and said self-refresh circuit, said power supply voltage having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein said second voltage level is smaller than said first voltage level.
Claim 3
Dependent Claim
57 words
The DRAM as claimed in claim 1, further comprising: pre-charge means for pre-charging bit lines with half of said first voltage level in the normal operation mode and with less than half of said second voltage level in the self-refresh mode, wherein the bit lines are connected to the memory cells for reading or writing the data.
Claim 4
Dependent Claim
103 words
The DRAM as claimed in claim 1, further comprising: pre-charge means for pre-charging bit lines with half of said first voltage level in the normal operation mode and half of said second voltage level in the self-refresh mode, wherein the bit lines are connected to the memory cells for reading and writing data; and capacitors each connected to a corresponding one of the bit lines for absorbing charges of the bit lines in the self-refresh mode after said pre-charge means pre-charges the bit lines so that a voltage level of the bit lines can become lower than half of said second voltage level.
Claim 5
Dependent Claim
140 words
The DRAM as claimed in claim 1, further comprising: pre-charge means for pre-charging bit lines with half of said first voltage level in the normal operation mode and half of said second voltage level in the self-refresh mode, wherein the bit lines are pairs of a first bit line and a second bit line, each of said pairs being used for reading and writing data for a corresponding one of the memory cells, and said first bit line being connected to a corresponding one of the memory cells; and capacitors each connected to a corresponding one of the bit lines for absorbing a charge of said second bit line in the self-refresh mode after said pre-charge means pre-charges the bit lines so that a voltage level of said second bit line can become lower than half said second voltage level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |